Pre-Grant Publication Number: 20070174746
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Prior Art Detail
Summary / Description
| Summary / Description | Another description of the RAZOR architecture. Instead of a plurality of processors, it has one with a plurality of latches. This is better in some ways than the proposed architecture (since the overhead is smaller) , and it could be argued it is a small step, clear to those educated in the art, between 1 processors with two sets of latches, and two processors running in lockstep. |
Basic Information
| Type of Prior Art | Print Publication |
| Publication Title * | Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation |
| Author | Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, |
| ISBN | |
| Page Range | |
| Medium | Journal article |
| Publication Date * | December 1, 2003 |
| URL | http://www.eecs.umich.edu/~taus... |
Notes / To Do
| Notes | A later version of this paper specifically discusses the voltage control system in more detail. It loads an FPGA to do the control, which in many ways is similar to doing it in Hardware. But that one was published after the patent application, though su |
Excerpt
Excerpt Many of the parameters that affect voltage margin vary over
time. Temperature margins will track ambient temperatures and can
vary on-die with processing demands. Consequently, to optimize
energy conservation it is desirable to introduce a voltage control system
into the design. The voltage control system adjusts the supply
voltage based on monitored error rates. If the error rate is very low, it
could indicate circuit computation is finishing too quickly and voltage
should be lowered. Similarly, a low error rate could indicate
changes in the ambient environment (e.g., decreasing temperature),
giving additional opportunity to lower voltage. Increasing error
rates, on the other hand, indicate circuits are not meeting clock
period constraints and voltage should be increased. The optimal
error rate depends on a number of factors including the energy cost
of error recovery and overall performance requirements, but in general
it is a small non-zero error rate. |
Relevance
Claims
1
A method for software execution, comprising:
varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors; and
adjusting the core voltages of the plural processors within the operating range to tune the plural processors.
Relevance
This has two sets of latches, operating in lockstep, and determines the operating range from these. The method of implementing the control is not specified, so it could presumably be software or hardware.
This has two sets of latches, operating in lockstep, and determines the operating range from these. The method of implementing the control is not specified, so it could presumably be software or hardware.
Claim Chart
Some
2
The method of Claim 1 further comprising:
determining a first voltage value where the plural processors exhibit anomalies while executing instructions; and
determining a second voltage value where the plural processors exhibit failures while executing instructions.
Relevance
The article discusses at least two types of problems as the supply is lowered. First you get anomalies, which are OK, as long as they are seldom enough that the effort to correct them does not outweigh the savings from low voltage operation. If the operation to correct and error itself has too many errors, you can get a "panic", which is an outright failure that takes more drastic steps to correct. This corresponds to the "failure" of the claim.
The article discusses at least two types of problems as the supply is lowered. First you get anomalies, which are OK, as long as they are seldom enough that the effort to correct them does not outweigh the savings from low voltage operation. If the operation to correct and error itself has too many errors, you can get a "panic", which is an outright failure that takes more drastic steps to correct. This corresponds to the "failure" of the claim.
Claim Chart
All
3
The method of Claim 1 further comprising, adjusting the core voltages of the plural processors to increase performance of the plural processors while the plural processors operate in cycle-by-cycle lockstep.
Relevance
The article describes how if the voltage is insufficient, the performance is not enough, and the voltage must be raised.
The article describes how if the voltage is insufficient, the performance is not enough, and the voltage must be raised.
Claim Chart
All
4
The method of Claim 1 further comprising:
determining low-end and high-end voltages where the plural processors exhibit anomalies; and
using the low-end and high-end voltages to calculate the operating range.
Relevance
This article explicitly tunes the circuit to have some small level of anomalies. The high end voltage is not checked, but this is (a) not normally necessary, and (b) a straightforward extension if it is.
This article explicitly tunes the circuit to have some small level of anomalies. The high end voltage is not checked, but this is (a) not normally necessary, and (b) a straightforward extension if it is.
Claim Chart
Some
6
The method of Claim 1 further comprising, operating the plural processors under full load to determine the operating range.
Relevance
Full load is a condition like any other to the methods of this paper.
Full load is a condition like any other to the methods of this paper.
Claim Chart
All
7
The method of Claim 1 further comprising, raising and lowering the core voltages of the plural processors to determine voltages where failures occur in order to calculate the operating range.
Relevance
The article explicitly does this.
The article explicitly does this.
Claim Chart
All
