Pre-Grant Publication Number: 20070118696
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Prior Art Detail
Summary / Description
| Summary / Description | For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early. |
Basic Information
| Type of Prior Art | Print Publication |
| Publication Title * | Understanding the Backward Slices of Performance Degrading Instructions |
| Author | Craig B. Zilles and Gurindar S. Sohi |
| ISBN | |
| Page Range | |
| Medium | Journal article |
| Publication Date * | June 1, 2000 |
| URL | |
Notes / To Do
| Notes | |
Excerpt
Excerpt For many applications, branch mispredictions and cache misses
limit a processor's performance to a level well below its peak
instruction throughput. A small fraction of static instructions,
whose behavior cannot be anticipated using current branch
predictors and caches, contribute a large fraction of such
performance degrading events. This paper analyzes the dynamic
instruction stream leading up to these performance degrading
instructions to identify the operations necessary to execute them
early. The backward slice (the subset of the program that relates to
the instruction) of these performance degrading instructions, if
small compared to the whole dynamic instruction stream, can be
pre-executed to hide the instruction's latency. To overcome
conservative dependence assumptions that result in large slices,
speculation can be used, resulting in speculative slices.
This paper provides an initial characterization of the backward
slices of L2 data cache misses and branch mispredictions, and
shows the effectiveness of techniques, including memory
dependence prediction and control independence, for reducing the
size of these slices. Through the use of these techniques, many
slices can be reduced to less than one tenth of the full dynamic
instruction stream when considering the 512 instructions before
the performance degrading instruction. |
Relevance
Claims
1
An apparatus comprising:
a register tracker to generate a pre-computation slice; and
a pre-computation engine to execute the pre-computation slice.
Relevance
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This paper looks to be one of the first publications on the topic
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