Pre-Grant Publication Number: 20070118658
Please help the USPTO examine the application by evaluating the relevance of the publicly submitted prior art to the patent application.
Peer-to-Patent forwards the Top 10 most relevant prior art submissions and their annotations to the United States Patent and Trademark Office.
Review this prior art and click on the thumbs up (or down) to indicate whether this submission should be forwarded to the USPTO.
If you login then you can add an annotation by typing in the box at the bottom of the screen to comment on the relevance of the prior art to the claims of the patent application.
Review this prior art and click on the thumbs up (or down) to indicate whether this submission should be forwarded to the USPTO.
If you login then you can add an annotation by typing in the box at the bottom of the screen to comment on the relevance of the prior art to the claims of the patent application.
Prior Art Detail
Summary / Description
| Summary / Description | This patent describes a method to detect errors in the BIOS during the POST process. When an error is detected, the user can be alerted via a pager. |
Basic Information
| Type of Prior Art | Issued Patents - US |
| Country | United States of America |
| Patent/Application # | 5390324 |
| Kind Code | United States (US) - United STATES Patent - A |
| Patentee Name | David M. Burckhartt, Lazaro D. Perez, Theodore F. Emerson, Randolph O. Dow, Gary A. Stimac |
| Relevant Pages, Columns, or Lines | Astract, Claim 1, Claim 3 |
| URL | http://www.google.com/patents?i... |
| Filing Date | October 2, 1992 |
| Additional Information | |
Notes / To Do
| Notes | |
Excerpt
Excerpt Provided in Claims section |
Relevance
Claims
1
A computer system, comprising:
a processor;
a basic input/output system (BIOS) including logic instructions which, when executed by the processor, configure the processor to:
initiate power on self test (POST) processing in the basic input/output system of a computing device;
present one or more management alert formats in a user interface;
receive a selection signal from the user interface identifying one of the management alert formats presented in the user interface; and
configure a device coupled to the computing system with the identified management alert format.
Relevance
The user is able to configure their alert in the BIOS, but it is limited to certain types of notification methods (pagers).
The user is able to configure their alert in the BIOS, but it is limited to certain types of notification methods (pagers).
Claim Chart
Some
6
A method, comprising:
initiating power on self test (POST) processing in the basic input/output system (BIOS) of a computing device;
presenting one or more management alert formats in a user interface;
receiving a selection signal from the user interface identifying one of the management alert formats presented in the user interface; and
configuring a device coupled to the computing system with the identified management alert format.
Relevance
Errors are detected during POST and the user is notified.
Errors are detected during POST and the user is notified.
Claim Chart
Some
