Pre-Grant Publication Number: 20080098157
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Prior Art Detail
Summary / Description
| Summary / Description | Patent on arrnagement and methods for the management of data in blocks of non volatile memory |
Basic Information
| Type of Prior Art | Issued Patents - US |
| Country | United States of America |
| Patent/Application # | 7,360,039 |
| Kind Code | United States (US) - United STATES Patent - A |
| Patentee Name | Eduard de Jong & Jurjen Bos |
| Relevant Pages, Columns, or Lines | abstract |
| URL | |
| Filing Date | June 21, 2004 |
| Additional Information | |
Notes / To Do
| Notes | |
Excerpt
Excerpt ... supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for uniquely identifying the oldest version, and (b) at least a most recently updated version of the set of data in a second, distinct memory area, the second memory area including at least one second tag for uniquely identifying the most recently updated version. The invention also relates to a computer arrangement including a processor and such a computer-readable medium, as well as to a method of updating sets of data having such tagged-data structures. |
Relevance
Claims
1
A non-volatile memory system comprising:
block-accessible non-volatile memory;
random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor; and
logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory;
wherein the logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.
Relevance
The art discloses the use of non-volatile memory in blocks, which the art calls 'pages'
The description states :
<cite> The interface 52, 54 and associated logic unit 50 may be implemented in hardware.</cite> and hence discloses that the memory controlling and accessing logic can be embodied in hardware.
claim 22 in the art discloses the use of non-volatile memory as source of data copied to non-volatile memory.
Figure 1 discloses the use of separate hardware logic to control the non-volatile memory and shows the non volatile memory as distinct from random access memory
The art discloses the use of non-volatile memory in blocks, which the art calls 'pages'
The description states :
<cite> The interface 52, 54 and associated logic unit 50 may be implemented in hardware.</cite> and hence discloses that the memory controlling and accessing logic can be embodied in hardware.
claim 22 in the art discloses the use of non-volatile memory as source of data copied to non-volatile memory.
Figure 1 discloses the use of separate hardware logic to control the non-volatile memory and shows the non volatile memory as distinct from random access memory
Claim Chart
All
2
A memory system according to Claim 1, further comprising logic arranged to initialize the memory system, comprising logic arranged to copy contents of the non-volatile, block-accessible memory to the random access memory.
Relevance
all of the art
all of the art
Claim Chart
All
3
A memory system according to Claim 1, wherein the non-volatile, block-accessible memory is flash memory.
Relevance
The art in the section of the field of invention indicates that it is applicable to different types of non-volatile memory: <cite> with non-volatile silicon devices, such as EEPROM, Flash-EPROM</cite> and repeated in the section of the objectives of the invention.
The art in the section of the field of invention indicates that it is applicable to different types of non-volatile memory: <cite> with non-volatile silicon devices, such as EEPROM, Flash-EPROM</cite> and repeated in the section of the objectives of the invention.
Claim Chart
All
4
A memory system according to Claim 1, wherein the block-accessible memory is larger than the random access memory that is written to the block-accessible memory, and wherein the logic arranged to write is arranged to write from the random access memory to vacant blocks of the block-accessible memory and to write to the block-accessible memory metadata enabling the most recently written copy of a part of the random access memory to be identified.
Relevance
The art discloses the use of meta data in blocks of non-volatile memory to identify the most recent version of data stored in an non-volatile memory that relates to data in another memory and the update of non-volatile memory with a newer version.
The art covers the functional aspects of the claim
The art discloses the use of meta data in blocks of non-volatile memory to identify the most recent version of data stored in an non-volatile memory that relates to data in another memory and the update of non-volatile memory with a newer version.
The art covers the functional aspects of the claim
Claim Chart
All
5
A memory system according to Claim 1, further comprising at least one logic device independent of the processor comprising at least part of the logic arranged to write from the random access memory to the block-accessible memory.
Relevance
see comments to claim 1.
see comments to claim 1.
Claim Chart
All
6
A memory system according to Claim 1, further comprising an integrated circuit package containing at least two of the random access memory, the non-volatile memory, and the logic.
Relevance
the art claim 17 discloses that the non-volatile memory management can be embodied by a smart card which is a single silicon device comprising the various memory devices
the art claim 17 discloses that the non-volatile memory management can be embodied by a smart card which is a single silicon device comprising the various memory devices
Claim Chart
All
7
A non-volatile memory system according to Claim 1, wherein in operation the random access memory contains a complete copy of current contents of the memory system, and wherein the block-accessible memory contains copies of all parts of the contents of the memory system other than parts that have been altered in the random access memory and await writing to the block-accessible memory.
Relevance
all of the art
all of the art
Claim Chart
Some
8
A memory system according to Claim 7, wherein:
the block-addressable memory is larger than the random access memory;
the logic is arranged to write blocks of the content of the random access memory to vacant blocks of the non-volatile, block-accessible memory; and the logic is arranged to write to the non-volatile memory metadata enabling a most recent copy of each block of the random access memory to be identified.
Relevance
as described for claim 4
as described for claim 4
Claim Chart
All
9
A memory system according to Claim 8, further comprising logic arranged to read the most recent copy of each block from the non-volatile memory and write such content to the random access memory in order to initialize the random access memory.
Relevance
the art claim 24 discloses that the random access memory is initialized with the most recent version from the non-volatile memory
the art claim 24 discloses that the random access memory is initialized with the most recent version from the non-volatile memory
Claim Chart
All
10
A computer system comprising:
a processor;
random access memory, wherein the processor is arranged to address the random access memory solely as part of the processor's random access memory address space;
non-volatile, block-addressable memory; and
logic arranged in normal operation to address said random access memory in blocks and to write the content of blocks of the random access memory including data that have been written by the processor to blocks of the non-volatile, block-accessible memory.
Relevance
the art figure 1, see comment on claim 1
the art figure 1, see comment on claim 1
Claim Chart
All
11
A computer system according to Claim 10, further comprising logic arranged to read contents of blocks of the non-volatile, block-accessible memory to the random access memory after an event that causes loss of the contents of the random access memory.
Relevance
In smart "cards tearing" is a well know technical issue, which is the type of event that causes loss of content of the volatile memory.
The art in its summary states:
<cite>Such atomic updates guarantee either a complete replacement of the data or unmodified previously stored data, even if the update operation is disrupted.</cite> clearly referring to an event as described in the claim and to restoring volatile memory form the data stored in non-volatile memory.
In smart "cards tearing" is a well know technical issue, which is the type of event that causes loss of content of the volatile memory.
The art in its summary states:
<cite>Such atomic updates guarantee either a complete replacement of the data or unmodified previously stored data, even if the update operation is disrupted.</cite> clearly referring to an event as described in the claim and to restoring volatile memory form the data stored in non-volatile memory.
Claim Chart
All
12
A computer system according to Claim 11, wherein the logic comprises logic arranged to initialize the random access memory after the event that causes loss of the contents thereof by reading from the block-accessible memory and writing to the random access memory a most recent copy of each part of the random access memory.
Relevance
claim 24 of the art.
and comments to claim 11
claim 24 of the art.
and comments to claim 11
Claim Chart
All
14
A method of maintaining a set of data, comprising:
providing random-access memory (RAM) containing the set of data;
permitting a processor to address the RAM linearly solely as part of the processor's random access memory address space and to read from and write to the RAM data forming parts of the set of data;
providing block-accessible non-volatile memory (NVM) at least as large as the RAM; and
writing from the RAM to the NVM blocks of data including data that have been written to the RAM by the processor.
Relevance
all of the art.
all of the art.
Claim Chart
All
15
A method according to Claim 14, further comprising initializing blocks of the RAM by reading blocks of data from the NVM.
Relevance
see comments to claim 12
see comments to claim 12
Claim Chart
All
16
A method according to Claim 15, further comprising initializing the RAM by reading from the NVM blocks of data containing the whole set of data.
Relevance
see comments to claim 12
see comments to claim 12
Claim Chart
Some
17
A method according to Claim 14, wherein the NVM is larger than the RAM, further comprising dividing the RAM into pages corresponding in size to blocks of NVM, wherein writing to the NVM comprises writing pages from the RAM to vacant blocks in the NVM, and further comprising reading from the NVM to the RAM, wherein the reading includes identifying and reading a most recent copy in the NVM of a RAM page.
Relevance
all of the art.
all of the art.
Claim Chart
Some
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