Pre-Grant Publication Number: 20080046686
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Prior Art Detail
Summary / Description
| Summary / Description | According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand. |
Basic Information
| Type of Prior Art | Issued Patents - US |
| Country | United States of America |
| Patent/Application # | US20060227966A1 |
| Kind Code | United States (US) - Patent Appl. Publ. within the ... - A1 |
| Patentee Name | Knowles, Simon; Bath, United Kingdom |
| Relevant Pages, Columns, or Lines | fig2, claims 1... |
| URL | |
| Filing Date | April 5, 2005 |
| Additional Information | |
Notes / To Do
| Notes | |
Excerpt
Excerpt Abstract
According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand. |
Relevance
Claims
1
A processor that processes Single Instruction Multiple Data (SIMD) instructions, which processor comprises:
an Instruction Fetch Unit that loads a SIMD instruction and applies it as input to a SIMD Instruction Decode Unit; and wherein
the SIMD Instruction Decode Unit decodes the applied SIMED instruction and produces output signals including: (a) SIMD field width identification signals; (b) SIMD source operand identification signals; and (c) SIMD half-operand modifier signals.
Relevance
Claim 1 of disclosure essentially describes a system where the decode unit initiate a register fetch (fig 22, box 260) followed by formatting (in box 240). The formatting mentioned in disclosure is essentially handling half size values. For the “high”, one simply take the upper bits and shift them to the lower positions; for the “low”, one simply nix (and with bits 0) the upper bits.
This formatting functionality can be performed with a “permute logic” (see IBM VMX instruction set architecture, referred in the disclosure). By selecting the desired bits in the input logic of a permute (i.e. the high or low bits) and placing them in the desired position (i.e. the low bit), we essentially perform the disclosed processing for high/low with a permute instead of a shift or and-with-bit-zero. Thus there is no functional difference between using a permute logic or the shift/and approach. In fact, it is trivial to come up with the permute patterns that are needed to implement a specific handling of high or low disclosed here. Note that permute logic such as present in the Cell BE/SPE architecture [Power Efficient Processor Architecture and The Cell Processor, Hofstee, HPCA-11 2005] has a permute logic that can insert specific constants such as zero needed here.
The formatted data is then shipped to the execution unit (box 270 of fig 22). Knowles proposes exactly this scheme (see Knowles’ fig 2, box 202). The fact that this disclosure ships the operands 225 (in fig 22) first to box 240 instead of directly to 245 is meaningless, as no processing is done with the operand descriptor 225 prior to be shipped by wire 245 to box 260. Thus the scheme proposed here is entirely covered by Knowles.
While most permute logic cannot handle bit-level permute granularity, it is a trivial extension to extend a logic that permute individual byte quantities (such as the VMX permute logic) to bit quantities.
Claim 1 of disclosure essentially describes a system where the decode unit initiate a register fetch (fig 22, box 260) followed by formatting (in box 240). The formatting mentioned in disclosure is essentially handling half size values. For the “high”, one simply take the upper bits and shift them to the lower positions; for the “low”, one simply nix (and with bits 0) the upper bits.
This formatting functionality can be performed with a “permute logic” (see IBM VMX instruction set architecture, referred in the disclosure). By selecting the desired bits in the input logic of a permute (i.e. the high or low bits) and placing them in the desired position (i.e. the low bit), we essentially perform the disclosed processing for high/low with a permute instead of a shift or and-with-bit-zero. Thus there is no functional difference between using a permute logic or the shift/and approach. In fact, it is trivial to come up with the permute patterns that are needed to implement a specific handling of high or low disclosed here. Note that permute logic such as present in the Cell BE/SPE architecture [Power Efficient Processor Architecture and The Cell Processor, Hofstee, HPCA-11 2005] has a permute logic that can insert specific constants such as zero needed here.
The formatted data is then shipped to the execution unit (box 270 of fig 22). Knowles proposes exactly this scheme (see Knowles’ fig 2, box 202). The fact that this disclosure ships the operands 225 (in fig 22) first to box 240 instead of directly to 245 is meaningless, as no processing is done with the operand descriptor 225 prior to be shipped by wire 245 to box 260. Thus the scheme proposed here is entirely covered by Knowles.
While most permute logic cannot handle bit-level permute granularity, it is a trivial extension to extend a logic that permute individual byte quantities (such as the VMX permute logic) to bit quantities.
Claim Chart
All
2
The processor of Claim 1 that further comprises a SIMD Operand Fetch Unit that loads SIMD operand values wherein:
the SIMD field width identification signals, SIMD source operand identification signals and SIMD half-operand modifier signals are supplied as input to the SIMD Operand Fetch Unit;
in response to the SIMD source operand identification signals, the SIMD Operand Fetch Unit loads operand values;
n response to the SIMD field-width identification signals and the SIMD half-operand modifier signals, the SIMD Operand Fetch Unit applies half-operand modifications indicated by the SIMD half-operand modifier signals to the operand values to form output operand values; and
the SIMD Operand Fetch Unit outputs the output operand values.
Relevance
Claims 2 & 3 in this disclosure describe how the formatting is performed; this would correspond to signal to the permute logic in Knowles, and thus is prior art.
Claims 2 & 3 in this disclosure describe how the formatting is performed; this would correspond to signal to the permute logic in Knowles, and thus is prior art.
Claim Chart
All
3
The processor of Claim 2 wherein the SIMD half-operand modifier signals comprise two signals for each operand, the first signal h having a first value whenever a high half-operand modification is to be applied to the operand value and another value otherwise, and the second signal having a first value whenever a low half-operand modification is to be applied to the operand value and another value otherwise.
Relevance
Claims 2 & 3 in this disclosure describe how the formatting is performed; this would correspond to signal to the permute logic in Knowles, and thus is prior art.
Claims 2 & 3 in this disclosure describe how the formatting is performed; this would correspond to signal to the permute logic in Knowles, and thus is prior art.
Claim Chart
All
5
The method of Claim 4 wherein:
the half-operand modification may be either a high half operand modification or a low half operand modification;
the high half-operand modification selects only the high n/2 bits of each n-bit field; and
the low half-operand modification selects only the low n/2 bits of each field.
Relevance
Claim 5 in this disclosure describe how to implement formatting. Knowles performs precisely this operation using its permute logic.
Claim 5 in this disclosure describe how to implement formatting. Knowles performs precisely this operation using its permute logic.
Claim Chart
All
