Pre-Grant Publication Number: 20070283129
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Prior Art Detail
Summary / Description
| Summary / Description | If would seem that the current invention is a specific instance of IF logic, and a special case of logic first appearing in the IBM 360's TRT (TRanslate and Test) instruction. |
Basic Information
| Type of Prior Art | Online Publication |
| URL | http://www.research.ibm.com/jou... |
| Author/Creator | E. M. Schwarz, M. A. Check, C.-L. K. Shum, T. Koehler, S. B. Swaney, J. D. MacDougall, and C. A. Kry |
| Title | The microarchitecture of the IBM eServer z900 processor |
| Publication Date | January 1, 2002 |
| Publisher | IBM |
| Directions to Document Location | |
| Additional Information | Although this document describes the zSeries processor, TRT first appeared in the 360s, on or about 1963. TRT deals with a vector of 8 to 2048 bits. |
Notes / To Do
| Notes | |
Excerpt
Excerpt Character translations
The z/Architecture defines… TRT… for translating an input stream of single-byte characters bytewise into an output stream… by means of a 256-byte translation table. …
Coprocessor implementation
Predecessor processors of the z900 had implemented data compression and character translates mainly in millicode… Increasing performance requirements for data compression were the main reason for the choice of a coprocessor-based implementation. In addition, the hardware assists for data compression and character translations or “translates” in the processor turned out to severely restrict efforts for further reduction of logical path lengths. |
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Claims
1
A method comprising:
receiving a vector length (VL) value; and
generating a first number of micro-operations (μops) if the VL value is equal to or less than a first value and generating a second number μops if the VL value is greater than the first value.
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10
A computer system comprising:
a main memory device to store a first and second instruction, each of which to be decoded into at least one μop having a corresponding vector length (VL) value, and
a central processing unit (CPU) to fetch the first instruction and to retire a first number of uops in response to decoding the second instruction, wherein the first number of uops depends upon the VL value of the at least one μop corresponding to the first instruction.
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16
A central processing unit (CPU) comprising:
an execution unit to execute a VL writer μop to set a VL value;
a vector length (VL) tracker to cause a first number of μops to be generated if the VL value is within a first range of values and to cause a second number of μops to be generated if the VL value is within a second range of values.
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23
An article of manufacture including one or more computer readable media that embody a program of instructions, wherein the program of instructions, when executed by a processing unit, causes the processing unit to perform the process of:
receiving a vector length (VL) value; and
generating a first number of micro-operations (μops) if the VL value is equal to or less than a first value and generating a second number μops if the VL value is greater than the first value.
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