Pre-Grant Publication Number: 20070233761
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Prior Art Detail
Summary / Description
| Summary / Description | The reference describes a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks (or crossbars). Further the reference describes that nanowire junction arrays (crossbars) have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computations. |
Basic Information
| Type of Prior Art | Online Publication |
| URL | http://www.sciencemag.org/cgi/c... |
| Author/Creator | Yu Huang, Xiangfeng Duan, Yi Cui, Lincoln J. Lauhon, Kyoung-Ha Kim, Charles M. Lieber |
| Title | Logic Gates and Computation from Assembled Nanowire Building Blocks |
| Publication Date | November 9, 2001 |
| Publisher | Science Magazine |
| Directions to Document Location | Vol. 294. no. 5545, pp. 1313 - 1317 |
| Additional Information | |
Notes / To Do
| Notes | |
Excerpt
Excerpt Page 2, Para 2: "Semiconductor nanowires (NWs) have also been used as building blocks for assembling a range of nanodevices including FETs (12, 13), p-n diodes (13, 14), bipolar junction transistors, and complementary inverters (14)."
Page 4, Para 3: "Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY." |
Relevance
Claims
1
A computing device comprising:
at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
a programming unit configured to program the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
an input unit configured to provide a bit pattern representative of an input numerical value to the columns of the crossbar array; and
a post-processing unit configured to convert analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."
Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."
Claim Chart
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2
The computing device of Claim 1, wherein the at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."
Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."
Claim Chart
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6
The computing device of Claim 1, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”
Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”
Claim Chart
All
7
The computing device of Claim 1, wherein the at least one crossbar array includes a plurality of cascaded crossbar arrays and consecutive crossbar arrays are connected by an interface circuit.
Relevance
Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”
Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”
Claim Chart
Some
9
The computing device of Claim 1, wherein a plurality of the columns of the at least one crossbar array each stores a separate programmed numerical value and the output numerical value is a sum of a selected subset of the programmed numerical values wherein the selected subset is dependent on the input numerical value.
Relevance
Page 4, Para 3: "Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY."
Page 4, Para 3: "Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY."
Claim Chart
Some
11
A method comprising:
providing at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
programming the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
inputting a bit pattern representative of an input numerical value to the columns of the crossbar array; and
converting analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."
Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."
Claim Chart
All
12
The method of Claim 11, wherein the provided at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."
Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."
Claim Chart
All
16
The method of Claim 11, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”
Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”
Claim Chart
All
17
The method of Claim 11, wherein the step of providing of at least one crossbar array includes providing a plurality of cascaded crossbar arrays and providing interface circuitry connecting consecutive crossbar arrays.
Relevance
Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”
Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”
Claim Chart
Some
19
The method of Claim 11, including the step of performing an addition process using the at least one crossbar array.
Relevance
Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."
Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."
Claim Chart
All
