Pre-Grant Publication Number: 20070233761
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Prior Art Detail
Summary / Description
| Summary / Description | A crossbar memory unit with crosspoints programmable to low and high conductive states such that the crossbar array stores a bit pattern is disclosed. |
Basic Information
| Type of Prior Art | Online Publication |
| URL | http://www.iop.org/EJ/abstract/... |
| Author/Creator | Yong Chen, Gun-Young Jung, Douglas A A Ohlberg, Xuema Li, Duncan R Stewart, Jan O Jeppesen, Kent A N |
| Title | Nanoscale molecular-switch crossbar circuits |
| Publication Date | March 20, 2003 |
| Publisher | Nanotechnology, 2003 (IOP) |
| Directions to Document Location | Issue 4 (April 2003) |
| Additional Information | |
Notes / To Do
| Notes | Although a crossbar arrangement is disclosed in this prior art, an arithmetic processor is not described in this art. The art provides decoder arrangement to communicate with any processor/logic circuit to access the memory being stored in the crossbar ar |
Excerpt
Excerpt Page 3, Para 4: "The results of writing and reading all the bits in a ‘defect-free’ 8×8 crossbar memory can be seen in figure 3(b). The actual value for the low-resistance state (0) and the high-resistance state (1) varied between 10^6–5 × 10^8 and >4 × 10^9, respectively. In fact, it was still easy in the case of this 8 × 8 crossbar to distinguish a low bit from a high bit, because the highest low bit (~5×10^8) was still much lower in resistance than the lowest high bit (>4 × 10^9). As a demonstration, this 64-bit memory was used to store the word ‘HPinvent’ with standard ASCII characters (figure 3(b))." |
Relevance
Claims
1
A computing device comprising:
at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
a programming unit configured to program the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
an input unit configured to provide a bit pattern representative of an input numerical value to the columns of the crossbar array; and
a post-processing unit configured to convert analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
Figures 3 and 4 describe nanowires based crossbar circuits storing programmed bits. Page 3, Para 4: "The results of writing and reading all the bits in a ‘defect-free’ 8×8 crossbar memory can be seen in figure 3(b). The actual value for the low-resistance state (0) and the high-resistance state (1) varied between 10^6–5 × 10^8 and >4 × 10^9, respectively. In fact, it was still easy in the case of this 8 × 8 crossbar to distinguish a low bit from a high bit, because the highest low bit (~5×10^8) was still much lower in resistance than the lowest high bit (>4 × 10^9). As a demonstration, this 64-bit memory was used to store the word ‘HPinvent’ with standard ASCII characters (figure 3(b))."
Figures 3 and 4 describe nanowires based crossbar circuits storing programmed bits. Page 3, Para 4: "The results of writing and reading all the bits in a ‘defect-free’ 8×8 crossbar memory can be seen in figure 3(b). The actual value for the low-resistance state (0) and the high-resistance state (1) varied between 10^6–5 × 10^8 and >4 × 10^9, respectively. In fact, it was still easy in the case of this 8 × 8 crossbar to distinguish a low bit from a high bit, because the highest low bit (~5×10^8) was still much lower in resistance than the lowest high bit (>4 × 10^9). As a demonstration, this 64-bit memory was used to store the word ‘HPinvent’ with standard ASCII characters (figure 3(b))."
Claim Chart
Some
2
The computing device of Claim 1, wherein the at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
Page 3, below Fig. 3, explaining Fig. 3(b): "...The resistances of the cross points representing ‘0’ states, which ranged between 106 and 5 × 108 , are shown in the bottom half of the plot; the resistances of the cross points representing ‘1’ states, which are >4 × 109 , are shown in the top half of the diagram. The bit state at each cross point is indicated by a ‘0’ or ‘1’ in figure 3(a)."
Page 3, below Fig. 3, explaining Fig. 3(b): "...The resistances of the cross points representing ‘0’ states, which ranged between 106 and 5 × 108 *, are shown in the bottom half of the plot; the resistances of the cross points representing ‘1’ states, which are >4 × 109 *, are shown in the top half of the diagram. The bit state at each cross point is indicated by a ‘0’ or ‘1’ in figure 3(a)."
Claim Chart
All
6
The computing device of Claim 1, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
Page 1, Para 2: “To satisfy all three of the above requirements, we have proposed nanoscale circuits based on a configurable crossbar architecture to connect molecular switches [15–17] in a two-dimensional grid (as shown schematically in figure 1(a)). A crossbar has several advantages. First, the wire dimensions can be scaled continuously down to molecular sizes, while the number of wires in the crossbar can be scaled up arbitrarily to form large-scale generic circuits that can be configured for memory and/or logic applications. Second, it requires only 2N communication wires to individually address 2N nanowires with a demultiplexer [17], which allows the nano-circuit to communicate efficiently with external circuits and systems, for example, CMOS.”
Page 1, Para 2: “To satisfy all three of the above requirements, we have proposed nanoscale circuits based on a configurable crossbar architecture to connect molecular switches [15–17] in a two-dimensional grid (as shown schematically in figure 1(a)). A crossbar has several advantages. First, the wire dimensions can be scaled continuously down to molecular sizes, while the number of wires in the crossbar can be scaled up arbitrarily to form large-scale generic circuits that can be configured for memory and/or logic applications. Second, it requires only 2N communication wires to individually address 2N nanowires with a demultiplexer [17], which allows the nano-circuit to communicate efficiently with external circuits and systems, for example, CMOS.”
Claim Chart
All
7
The computing device of Claim 1, wherein the at least one crossbar array includes a plurality of cascaded crossbar arrays and consecutive crossbar arrays are connected by an interface circuit.
Relevance
Page 4, Para 1: “To demonstrate a demultiplexer/multiplexer functionality integrated with memory in a single crossbar, we configured a defect-free 8 × 8 crossbar into a 4 × 4 crossbar memory and two 4 × 4 decoders for the demultiplexer/multiplexers by setting the resistances at specific cross points (table 1(a)), one to control the horizontal wires (E, F, G and H) and the other to control the vertical wires (5, 6, 7 and 8) in the memory (figure 4).”
Page 4, Para 1: “To demonstrate a demultiplexer/multiplexer functionality integrated with memory in a single crossbar, we configured a defect-free 8 × 8 crossbar into a 4 × 4 crossbar memory and two 4 × 4 decoders for the demultiplexer/multiplexers by setting the resistances at specific cross points (table 1(a)), one to control the horizontal wires (E, F, G and H) and the other to control the vertical wires (5, 6, 7 and 8) in the memory (figure 4).”
Claim Chart
All
9
The computing device of Claim 1, wherein a plurality of the columns of the at least one crossbar array each stores a separate programmed numerical value and the output numerical value is a sum of a selected subset of the programmed numerical values wherein the selected subset is dependent on the input numerical value.
Relevance
The crossbar array of Fig. 3 stores programmed values as described below. Page 3, below Fig. 3 "Figure 3. The crossbar as a 64-bit random access memory. (a) The ideal ‘write’ and ‘read’ modes for the memory. To write a bit, V is increased in increments of 0.5 from 3.5 V until the bit is written or V reaches 7 V, while keeping V = V/2 (in our actual circuit, the vertical nanowires were floating); to read a bit, V = 0.5, and V = 0."
The crossbar array of Fig. 3 stores programmed values as described below. Page 3, below Fig. 3 "Figure 3. The crossbar as a 64-bit random access memory. (a) The ideal ‘write’ and ‘read’ modes for the memory. To write a bit, V is increased in increments of 0.5 from 3.5 V until the bit is written or V reaches 7 V, while keeping V* = V/2 (in our actual circuit, the vertical nanowires were floating); to read a bit, V = 0.5, and V* = 0."
Claim Chart
Some
11
A method comprising:
providing at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
programming the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
inputting a bit pattern representative of an input numerical value to the columns of the crossbar array; and
converting analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
Figures 3 and 4 describe nanowires based crossbar circuits storing programmed bits. Page 3, Para 4: "The results of writing and reading all the bits in a ‘defect-free’ 8×8 crossbar memory can be seen in figure 3(b). The actual value for the low-resistance state (0) and the high-resistance state (1) varied between 10^6–5 × 10^8 and >4 × 10^9, respectively. In fact, it was still easy in the case of this 8 × 8 crossbar to distinguish a low bit from a high bit, because the highest low bit (~5×10^8) was still much lower in resistance than the lowest high bit (>4 × 10^9). As a demonstration, this 64-bit memory was used to store the word ‘HPinvent’ with standard ASCII characters (figure 3(b))."
Figures 3 and 4 describe nanowires based crossbar circuits storing programmed bits. Page 3, Para 4: "The results of writing and reading all the bits in a ‘defect-free’ 8×8 crossbar memory can be seen in figure 3(b). The actual value for the low-resistance state (0) and the high-resistance state (1) varied between 10^6–5 × 10^8 and >4 × 10^9, respectively. In fact, it was still easy in the case of this 8 × 8 crossbar to distinguish a low bit from a high bit, because the highest low bit (~5×10^8) was still much lower in resistance than the lowest high bit (>4 × 10^9). As a demonstration, this 64-bit memory was used to store the word ‘HPinvent’ with standard ASCII characters (figure 3(b))."
Claim Chart
Some
12
The method of Claim 11, wherein the provided at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
Page 3, below Fig. 3, explaining Fig. 3(b): "...The resistances of the cross points representing ‘0’ states, which ranged between 106 and 5 × 108 , are shown in the bottom half of the plot; the resistances of the cross points representing ‘1’ states, which are >4 × 109 , are shown in the top half of the diagram. The bit state at each cross point is indicated by a ‘0’ or ‘1’ in figure 3(a)."
Page 3, below Fig. 3, explaining Fig. 3(b): "...The resistances of the cross points representing ‘0’ states, which ranged between 106 and 5 × 108 *, are shown in the bottom half of the plot; the resistances of the cross points representing ‘1’ states, which are >4 × 109 *, are shown in the top half of the diagram. The bit state at each cross point is indicated by a ‘0’ or ‘1’ in figure 3(a)."
Claim Chart
All
16
The method of Claim 11, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
Page 1, Para 2: “To satisfy all three of the above requirements, we have proposed nanoscale circuits based on a configurable crossbar architecture to connect molecular switches [15–17] in a two-dimensional grid (as shown schematically in figure 1(a)). A crossbar has several advantages. First, the wire dimensions can be scaled continuously down to molecular sizes, while the number of wires in the crossbar can be scaled up arbitrarily to form large-scale generic circuits that can be configured for memory and/or logic applications. Second, it requires only 2N communication wires to individually address 2N nanowires with a demultiplexer [17], which allows the nano-circuit to communicate efficiently with external circuits and systems, for example, CMOS.”
Page 1, Para 2: “To satisfy all three of the above requirements, we have proposed nanoscale circuits based on a configurable crossbar architecture to connect molecular switches [15–17] in a two-dimensional grid (as shown schematically in figure 1(a)). A crossbar has several advantages. First, the wire dimensions can be scaled continuously down to molecular sizes, while the number of wires in the crossbar can be scaled up arbitrarily to form large-scale generic circuits that can be configured for memory and/or logic applications. Second, it requires only 2N communication wires to individually address 2N nanowires with a demultiplexer [17], which allows the nano-circuit to communicate efficiently with external circuits and systems, for example, CMOS.”
Claim Chart
All
17
The method of Claim 11, wherein the step of providing of at least one crossbar array includes providing a plurality of cascaded crossbar arrays and providing interface circuitry connecting consecutive crossbar arrays.
Relevance
Page 4, Para 1: “To demonstrate a demultiplexer/multiplexer functionality integrated with memory in a single crossbar, we configured a defect-free 8 × 8 crossbar into a 4 × 4 crossbar memory and two 4 × 4 decoders for the demultiplexer/multiplexers by setting the resistances at specific cross points (table 1(a)), one to control the horizontal wires (E, F, G and H) and the other to control the vertical wires (5, 6, 7 and 8) in the memory (figure 4).”
Page 4, Para 1: “To demonstrate a demultiplexer/multiplexer functionality integrated with memory in a single crossbar, we configured a defect-free 8 × 8 crossbar into a 4 × 4 crossbar memory and two 4 × 4 decoders for the demultiplexer/multiplexers by setting the resistances at specific cross points (table 1(a)), one to control the horizontal wires (E, F, G and H) and the other to control the vertical wires (5, 6, 7 and 8) in the memory (figure 4).”
Claim Chart
All
