Pre-Grant Publication Number: 20070233761
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Prior Art Detail
Summary / Description
| Summary / Description | The publication describes crossbar based nanoelectronics, CMOS/nano interface and CMOS interface circuitry. The publication further describes simulation of crossbar nano circuitry having logic and arithmetic implementations. |
Basic Information
| Type of Prior Art | Online Publication |
| URL | http://www.google.com/scholar?h... |
| Author/Creator | Ziegler, M.M. Stan, M.R. |
| Title | The CMOS/Nano Interface from a Circuits Perspective |
| Publication Date | May 28, 2003 |
| Publisher | Proceedings of the 2003 IEEE International Symposium on Circuits and Systems |
| Directions to Document Location | Volume: 4, page(s): IV-904- IV-907 |
| Additional Information | |
Notes / To Do
| Notes | |
Excerpt
Excerpt Abstract: "We consider a circuit paradigm that combines conventional silicon microelectronics with emerging self-assembled nanoelectronics. Peripheral CMOS circuitry is used to drive the input signals and restore the output signals of nanoscale crossbar structures. We address a number of issues dealing with interfacing CMOS and nanoelectronics. Furthermore, we consider important metrics, such as, delay, area, and energy for a full-adder implemented in the mixed circuit paradigm."
Page 2, Para 3: "The decoder and data array pair can be used for logic or memory. The decoder is equivalent to a plane of AND gates, while the data array is essentially a plane of OR gates. Thus, two-level logic representations can be easily mapped to the crossbar. Fig. 4 shows a schematic of a full-adder realized in a crossbar along with the truth table." |
Relevance
Claims
1
A computing device comprising:
at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
a programming unit configured to program the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
an input unit configured to provide a bit pattern representative of an input numerical value to the columns of the crossbar array; and
a post-processing unit configured to convert analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
Fig. 4 illustrates a full adder using nanowire crossbar technology.
Fig. 4 illustrates a full adder using nanowire crossbar technology.
Claim Chart
All
2
The computing device of Claim 1, wherein the at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
In Section II A, para 2, a crossbar array having a variable resitance layer is described. "The most commonly targeted regular structure for self-assembled nanoelectronics is a crossbar. Fig. 1 shows a typical nanoscale crossbar structure that consists of a lower plane of parallel nanowires crossed perpendicularly by an upper plane of nanowires A bistable junction exists between the wire crossings. The bistable junctions can be electrically altered to switch between a low resistance state (on-state) and a high resistance state (off-state)."
In Section II A, para 2, a crossbar array having a variable resitance layer is described. "The most commonly targeted regular structure for self-assembled nanoelectronics is a crossbar. Fig. 1 shows a typical nanoscale crossbar structure that consists of a lower plane of parallel nanowires crossed perpendicularly by an upper plane of nanowires A bistable junction exists between the wire crossings. The bistable junctions can be electrically altered to switch between a low resistance state (on-state) and a high resistance state (off-state)."
Claim Chart
All
6
The computing device of Claim 1, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
"This crossbar structure is a target for a variety physical implementations, such as, self-assembled nanowires, nanotubes, and nanoimprinted wires."
"This crossbar structure is a target for a variety physical implementations, such as, self-assembled nanowires, nanotubes, and nanoimprinted wires."
Claim Chart
All
7
The computing device of Claim 1, wherein the at least one crossbar array includes a plurality of cascaded crossbar arrays and consecutive crossbar arrays are connected by an interface circuit.
Relevance
Page 2, col 1, last paragraph describes consecutive crossbar arrays. "We consider a circuit paradigm that combines conventional silicon microelectronics with emerging self-assembled nanoelectronics. Peripheral CMOS circuitry is used to drive the input signals and restore the output signals of nanoscale crossbar structures. We address a number of issues dealing with interfacing CMOS and nanoelectronics. Furthermore, we consider important metrics, such as, delay, area, and energy for a full-adder implemented in the mixed circuit paradigm."
Page 2, col 1, last paragraph describes consecutive crossbar arrays. "We consider a circuit paradigm that combines conventional silicon microelectronics with emerging self-assembled nanoelectronics. Peripheral CMOS circuitry is used to drive the input signals and restore the output signals of nanoscale crossbar structures. We address a number of issues dealing with interfacing CMOS and nanoelectronics. Furthermore, we consider important metrics, such as, delay, area, and energy for a full-adder implemented in the mixed circuit paradigm."
Claim Chart
All
12
The method of Claim 11, wherein the provided at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
In Section II A, para 2, a crossbar array having a variable resitance layer is described. "The most commonly targeted regular structure for self-assembled nanoelectronics is a crossbar. Fig. 1 shows a typical nanoscale crossbar structure that consists of a lower plane of parallel nanowires crossed perpendicularly by an upper plane of nanowires A bistable junction exists between the wire crossings. The bistable junctions can be electrically altered to switch between a low resistance state (on-state) and a high resistance state (off-state)."
In Section II A, para 2, a crossbar array having a variable resitance layer is described. "The most commonly targeted regular structure for self-assembled nanoelectronics is a crossbar. Fig. 1 shows a typical nanoscale crossbar structure that consists of a lower plane of parallel nanowires crossed perpendicularly by an upper plane of nanowires A bistable junction exists between the wire crossings. The bistable junctions can be electrically altered to switch between a low resistance state (on-state) and a high resistance state (off-state)."
Claim Chart
All
16
The method of Claim 11, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
"This crossbar structure is a target for a variety physical implementations, such as, self-assembled nanowires, nanotubes, and nanoimprinted wires."
"This crossbar structure is a target for a variety physical implementations, such as, self-assembled nanowires, nanotubes, and nanoimprinted wires."
Claim Chart
All
17
The method of Claim 11, wherein the step of providing of at least one crossbar array includes providing a plurality of cascaded crossbar arrays and providing interface circuitry connecting consecutive crossbar arrays.
Relevance
“Fig. 3. A platform for logic and memory can be assembled by combining
a number of diagonal interface structures.”
“Fig. 8. The addition of a third plane of nanowires allows a column decoder
to included in the nano crossbar structure.”
“Fig. 3. A platform for logic and memory can be assembled by combining
a number of diagonal interface structures.”
“Fig. 8. The addition of a third plane of nanowires allows a column decoder
to included in the nano crossbar structure.”
Claim Chart
All
19
The method of Claim 11, including the step of performing an addition process using the at least one crossbar array.
Relevance
Fig. 4 illustrates a full adder using nanowire crossbar technology.
Fig. 4 illustrates a full adder using nanowire crossbar technology.
Claim Chart
All
