Pre-Grant Publication Number: 20070233761
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Prior Art Detail
Summary / Description
| Summary / Description | An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances. |
Basic Information
| Type of Prior Art | Issued Patents - US |
| Country | United States of America |
| Patent/Application # | US 2005/0258872 A1 |
| Kind Code | United States (US) - Patent Appl. Publ. within the ... - A1 |
| Patentee Name | Hewlett-Packard Development Company |
| Relevant Pages, Columns, or Lines | Col 4, Lines 19-30; Col 6, Lin |
| URL | http://appft1.uspto.gov/netacgi... |
| Filing Date | November 24, 2005 |
| Additional Information | |
Notes / To Do
| Notes | Note that this patent publication was granted on April 10, 2007 as US 7,203,789 B2. |
Excerpt
Excerpt Relevant excerpt is provided in the relevance section of the claim. |
Relevance
Claims
1
A computing device comprising:
at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
a programming unit configured to program the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
an input unit configured to provide a bit pattern representative of an input numerical value to the columns of the crossbar array; and
a post-processing unit configured to convert analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
[0045] "FIGS. 1A and 1B illustrate an example array 100 of nano-scale crossbar switches which define junctions that can be independently configured to behave as electronic devices. In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction. The nanowire arrays 102 and 104 may be either metal or semiconductor (e.g., silicon) wires, that are crossed at some non-zero angle defining the junction 108. The interlayer 106 is a thin layer of material with particular electrochemical properties, for example, rotaxane. The interlayer 106 can be discontinuous, e.g., a collection of molecules. Example materials that can be used for the interlayer 106 are described in U.S. Pat. No. 6,459,095, U.S. Pat. No. 6,624,002 and U.S. Pat. No. 6,674,932, which are incorporated herein by reference. Depending on the nature of the interlayer 106 and the type of wires 102 and 104 used, the junction 108 can be configured (and possibly unconfigured) by applying suitable voltages to the two wires that form it to implement an electronic device, such as a diode (FIG. 2A), a field effect transistor (FIGS. 2B and 2C), or a resistor (FIG. 2D). [0093] The efficiency of the crossbar can be further improved by adding additional minterms and output latches. To this end, FIG. 18 illustrates implementation of a half adder circuit in a crossbar 1800 according to an example embodiment. In this example, the half adder produces the sum and carry of two inputs, A and B."
[0045] "FIGS. 1A and 1B illustrate an example array 100 of nano-scale crossbar switches which define junctions that can be independently configured to behave as electronic devices. In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction. The nanowire arrays 102 and 104 may be either metal or semiconductor (e.g., silicon) wires, that are crossed at some non-zero angle defining the junction 108. The interlayer 106 is a thin layer of material with particular electrochemical properties, for example, rotaxane. The interlayer 106 can be discontinuous, e.g., a collection of molecules. Example materials that can be used for the interlayer 106 are described in U.S. Pat. No. 6,459,095, U.S. Pat. No. 6,624,002 and U.S. Pat. No. 6,674,932, which are incorporated herein by reference. Depending on the nature of the interlayer 106 and the type of wires 102 and 104 used, the junction 108 can be configured (and possibly unconfigured) by applying suitable voltages to the two wires that form it to implement an electronic device, such as a diode (FIG. 2A), a field effect transistor (FIGS. 2B and 2C), or a resistor (FIG. 2D). [0093] The efficiency of the crossbar can be further improved by adding additional minterms and output latches. To this end, FIG. 18 illustrates implementation of a half adder circuit in a crossbar 1800 according to an example embodiment. In this example, the half adder produces the sum and carry of two inputs, A and B."
Claim Chart
All
2
The computing device of Claim 1, wherein the at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
[0049] "The resistor crossbars are reconfigurable; their resistance abruptly changes when the voltage drop across them reaches a certain threshold. Moreover, the threshold for transitioning from low-to-high impedance is different from the threshold for high-to-low."
[0049] "The resistor crossbars are reconfigurable; their resistance abruptly changes when the voltage drop across them reaches a certain threshold. Moreover, the threshold for transitioning from low-to-high impedance is different from the threshold for high-to-low."
Claim Chart
All
6
The computing device of Claim 1, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
[0045] "In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction."
[0045] "In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction."
Claim Chart
All
7
The computing device of Claim 1, wherein the at least one crossbar array includes a plurality of cascaded crossbar arrays and consecutive crossbar arrays are connected by an interface circuit.
Relevance
[0051] "Referring to FIG. 4, a logic/latch cascade 400 according to an example embodiment includes latch elements 402, 406 and 410 and logic elements 404 and 408 configured as shown. In this example, input signals are latched, combined in logic to form additional signals which are then also latched. Data flows through the cascade 400 from left to right with each stage, whether logic or latch, being driven by clock signals in sequence in order to execute and propagate the computation." [0095] "More complex logic functions can be implemented by combining several crossbars, using some of the crossbars for implementing logic and some for implementing routing. By way of example, FIG. 19 illustrates an architecture 1900 including logic crossbars 1902 and 1904 and a routing crossbar 1906 configured as shown."
[0051] "Referring to FIG. 4, a logic/latch cascade 400 according to an example embodiment includes latch elements 402, 406 and 410 and logic elements 404 and 408 configured as shown. In this example, input signals are latched, combined in logic to form additional signals which are then also latched. Data flows through the cascade 400 from left to right with each stage, whether logic or latch, being driven by clock signals in sequence in order to execute and propagate the computation." [0095] "More complex logic functions can be implemented by combining several crossbars, using some of the crossbars for implementing logic and some for implementing routing. By way of example, FIG. 19 illustrates an architecture 1900 including logic crossbars 1902 and 1904 and a routing crossbar 1906 configured as shown."
Claim Chart
All
9
The computing device of Claim 1, wherein a plurality of the columns of the at least one crossbar array each stores a separate programmed numerical value and the output numerical value is a sum of a selected subset of the programmed numerical values wherein the selected subset is dependent on the input numerical value.
Relevance
[0093]"... To this end, FIG. 18 illustrates implementation of a half adder circuit in a crossbar 1800 according to an example embodiment. In this example, the half adder produces the sum and carry of two inputs, A and B."
[0093]"... To this end, FIG. 18 illustrates implementation of a half adder circuit in a crossbar 1800 according to an example embodiment. In this example, the half adder produces the sum and carry of two inputs, A and B."
Claim Chart
All
11
A method comprising:
providing at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
programming the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
inputting a bit pattern representative of an input numerical value to the columns of the crossbar array; and
converting analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
[0045] "FIGS. 1A and 1B illustrate an example array 100 of nano-scale crossbar switches which define junctions that can be independently configured to behave as electronic devices. In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction. The nanowire arrays 102 and 104 may be either metal or semiconductor (e.g., silicon) wires, that are crossed at some non-zero angle defining the junction 108. The interlayer 106 is a thin layer of material with particular electrochemical properties, for example, rotaxane. The interlayer 106 can be discontinuous, e.g., a collection of molecules. Example materials that can be used for the interlayer 106 are described in U.S. Pat. No. 6,459,095, U.S. Pat. No. 6,624,002 and U.S. Pat. No. 6,674,932, which are incorporated herein by reference. Depending on the nature of the interlayer 106 and the type of wires 102 and 104 used, the junction 108 can be configured (and possibly unconfigured) by applying suitable voltages to the two wires that form it to implement an electronic device, such as a diode (FIG. 2A), a field effect transistor (FIGS. 2B and 2C), or a resistor (FIG. 2D). [0093] The efficiency of the crossbar can be further improved by adding additional minterms and output latches. To this end, FIG. 18 illustrates implementation of a half adder circuit in a crossbar 1800 according to an example embodiment. In this example, the half adder produces the sum and carry of two inputs, A and B."
[0045] "FIGS. 1A and 1B illustrate an example array 100 of nano-scale crossbar switches which define junctions that can be independently configured to behave as electronic devices. In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction. The nanowire arrays 102 and 104 may be either metal or semiconductor (e.g., silicon) wires, that are crossed at some non-zero angle defining the junction 108. The interlayer 106 is a thin layer of material with particular electrochemical properties, for example, rotaxane. The interlayer 106 can be discontinuous, e.g., a collection of molecules. Example materials that can be used for the interlayer 106 are described in U.S. Pat. No. 6,459,095, U.S. Pat. No. 6,624,002 and U.S. Pat. No. 6,674,932, which are incorporated herein by reference. Depending on the nature of the interlayer 106 and the type of wires 102 and 104 used, the junction 108 can be configured (and possibly unconfigured) by applying suitable voltages to the two wires that form it to implement an electronic device, such as a diode (FIG. 2A), a field effect transistor (FIGS. 2B and 2C), or a resistor (FIG. 2D). [0093] The efficiency of the crossbar can be further improved by adding additional minterms and output latches. To this end, FIG. 18 illustrates implementation of a half adder circuit in a crossbar 1800 according to an example embodiment. In this example, the half adder produces the sum and carry of two inputs, A and B."
Claim Chart
All
12
The method of Claim 11, wherein the provided at least one crossbar array includes a resistance layer in which the resistance may be modified by application of a sufficient voltage or current.
Relevance
[0049] "The resistor crossbars are reconfigurable; their resistance abruptly changes when the voltage drop across them reaches a certain threshold. Moreover, the threshold for transitioning from low-to-high impedance is different from the threshold for high-to-low."
[0049] "The resistor crossbars are reconfigurable; their resistance abruptly changes when the voltage drop across them reaches a certain threshold. Moreover, the threshold for transitioning from low-to-high impedance is different from the threshold for high-to-low."
Claim Chart
All
16
The method of Claim 11, wherein the wires of the at least one crossbar array are formed from individual nanotubes or nanotube ribbons.
Relevance
[0045] "In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction."
[0045] "In this example, the array 100 of nano-scale crossbar switches is formed with two parallel planes of nanowire arrays (denoted nanowires 102 and 104, respectively) separated by an interlayer 106 as shown. In this example, the wires in one plane are orthogonal to the wires in the other, with each wire in a given plane being of the same type. The region where a wire in one plane crosses over a wire in the other is called a junction 108. A crossed wire switch or crossbar switch 110 is formed in each junction."
Claim Chart
All
17
The method of Claim 11, wherein the step of providing of at least one crossbar array includes providing a plurality of cascaded crossbar arrays and providing interface circuitry connecting consecutive crossbar arrays.
Relevance
[0051] "Referring to FIG. 4, a logic/latch cascade 400 according to an example embodiment includes latch elements 402, 406 and 410 and logic elements 404 and 408 configured as shown. In this example, input signals are latched, combined in logic to form additional signals which are then also latched. Data flows through the cascade 400 from left to right with each stage, whether logic or latch, being driven by clock signals in sequence in order to execute and propagate the computation." [0095] "More complex logic functions can be implemented by combining several crossbars, using some of the crossbars for implementing logic and some for implementing routing. By way of example, FIG. 19 illustrates an architecture 1900 including logic crossbars 1902 and 1904 and a routing crossbar 1906 configured as shown."
[0051] "Referring to FIG. 4, a logic/latch cascade 400 according to an example embodiment includes latch elements 402, 406 and 410 and logic elements 404 and 408 configured as shown. In this example, input signals are latched, combined in logic to form additional signals which are then also latched. Data flows through the cascade 400 from left to right with each stage, whether logic or latch, being driven by clock signals in sequence in order to execute and propagate the computation." [0095] "More complex logic functions can be implemented by combining several crossbars, using some of the crossbars for implementing logic and some for implementing routing. By way of example, FIG. 19 illustrates an architecture 1900 including logic crossbars 1902 and 1904 and a routing crossbar 1906 configured as shown."
Claim Chart
All
18
The method of Claim 11, including the step of performing a multiplication process using the at least one crossbar array.
Relevance
[0081] “The combination of the ability to compute the AND function along with the ability to invert signals with the latch provides the ability to perform universal computation: crossbars can be combined with latches to implement arbitrary logic.”
[0081] “The combination of the ability to compute the AND function along with the ability to invert signals with the latch provides the ability to perform universal computation: crossbars can be combined with latches to implement arbitrary logic.”
Claim Chart
All
19
The method of Claim 11, including the step of performing an addition process using the at least one crossbar array.
Relevance
[0081] “The combination of the ability to compute the AND function along with the ability to invert signals with the latch provides the ability to perform universal computation: crossbars can be combined with latches to implement arbitrary logic.”
[0081] “The combination of the ability to compute the AND function along with the ability to invert signals with the latch provides the ability to perform universal computation: crossbars can be combined with latches to implement arbitrary logic.”
Claim Chart
All
