Pre-Grant Publication Number: 20070233761
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Prior Art Detail
#122 POINT CONTACT ARRAY, NOT CIRCUIT, AND ELECTRONIC CIRCUIT COMPRISING THE SAME
Applies to Claims 1
Summary / Description
| Summary / Description | The publication discloses a computing device for performing arithmetical operations, using an array of programmable resistances. |
Basic Information
| Type of Prior Art | Issued Patents - US |
| Country | Japan |
| Patent/Application # | EP1331671A1 |
| Kind Code | European Patent Office (E... - Publ. of Application with sear... - A1 |
| Patentee Name | JAPAN SCIENCE AND TECHNOLOGY CORPORATION |
| Relevant Pages, Columns, or Lines | Pages 2,3 & 5. Figures 2, |
| URL | http://www.freepatentsonline.co... |
| Filing Date | July 30, 2003 |
| Additional Information | |
Notes / To Do
| Notes | |
Excerpt
Excerpt "In consideration of the above situations, a first object of the present invention is to provide a point contact array including a plurality of point contacts each of which electrically and reversibly controls conductance between electrodes and each of which is applicable to an arithmetic circuit, a logic circuit, and a memory device." (pp.2, paragraph 0013)
"[10] In the point contact array described in [8], preferably, the quantized conductance of each point contact is used as an input signal, and the potentials of the respective electrodes are controlled to perform addition or subtraction of the input signals." (pp.3,paragraph 0015)
"Fig. 4 shows the result of the arithmetic operation according to the second embodiment of the present invention. Below a graph, the inputted N 1 and N 2 and measured N out are shown so as to correspond to the abscissa axis of the graph. It is found that the obtained current I out has quantized conductance corresponding to (N 1 + N 2 ). In other words, the addition is correctly performed. According to the present embodiment, 16 addition results corresponding to N 1 = 0 to 3 and N 2 = 0 to 3 are shown in the same way as the first embodiment. Larger quantum numbers can also be used. For the number of point contacts used, namely, the number of inputs, three or more inputs can also be used." (pp.5, paragraph 0040) |
Relevance
Claims
1
A computing device comprising:
at least one crossbar array including a first set of N conductive parallel wires (N≧2) forming a set of columns and a second set of M conductive parallel wires (M≧2) forming a set of rows, and formed so as to intersect the first set of conductive parallel wires, wherein intersections are formed between the first and second sets of wires forming M×N crosspoints wherein each of the crosspoints is programmable so as to be in a relatively high conductive state representative of a binary value 1 or a relatively low conductive state representative of a binary value 0;
a programming unit configured to program the crosspoints to have one of the relatively high conductive state or the relatively low conductive state so that at least one column of the crossbar array stores a bit pattern representative of a programmed numerical value;
an input unit configured to provide a bit pattern representative of an input numerical value to the columns of the crossbar array; and
a post-processing unit configured to convert analog signals output from each of the rows of the crossbar array into digital output bit patterns and configured to combine the digital output bit patterns so as to form a resultant bit pattern representative of an output numerical value,
wherein the output numerical value is mathematically dependent on both the programmed numerical value and the input numerical value.
Relevance
EP1331671A1 discloses a computing device for performing arithmetical operations, using an array of programmable resistances.
EP1331671A1 discloses a computing device for performing arithmetical operations, using an array of programmable resistances.
Claim Chart
All
