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ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTRUCTION PROCESSING (E.G., PROCESSORS)

Sub-classifications for 712
ClassificationsCodeApplicationsSubscribe
 
PROCESSING ARCHITECTURE712/0010001
 
Vector processor712/0020000
 
Scalar/vector processor interface712/0030000
 
Distributing of vector data to vector registers712/0040001
 
Masking to control an access to data in vector register712/0050000
 
Controlling access to external vector data712/0060000
 
Vector processor operation712/0070000
 
Sequential712/0080000
 
Concurrent712/0090000
 
Array processor712/0100000
 
Array processor element interconnection712/0110000
 
Cube or hypercube712/0120000
 
Partitioning712/0130000
 
Processing element memory712/0140000
 
Reconfiguring712/0150000
 
Array processor operation712/0160000
 
Application specific712/0170000
 
Data flow array processor712/0180000
 
Systolic array processor712/0190000
 
Multimode (e.g., MIMD to SIMD, etc.)712/0200000
 
Multiple instruction, Multiple data (MIMD)712/0210000
 
Single instruction, multiple data (SIMD)712/0220001
 
Superscalar712/0230000
 
Long instruction word712/0240000
 
Data driven or demand driven processor712/0250000
 
Detection/pairing based on destination, ID tag, or data712/0260000
 
Particular data driven memory structure712/0270000
 
Distributed processing system712/0280000
 
Interface712/0290000
 
Operation712/0300000
 
Master/slave712/0310000
 
Microprocessor or multichip or multimodule processor having sequential program control712/0320000
 
Having multiple internal buses712/0330000
 
Including coprocessor712/0340000
 
Digital Signal processor712/0350000
 
Application specific712/0360000
 
Programmable (e.g., EPROM)712/0370000
 
Offchip interface712/0380000
 
Externally controlled internal mode switching via pin712/0390000
 
External sync or interrupt signal712/0400000
 
RISC712/0410000
 
Operation712/0420000
 
Mode switching712/0430000
 
ARCHITECTURE BASED INSTRUCTION PROCESSING712/2000000
 
Data flow based system712/2010000
 
Stack based computer712/2020000
 
Multiprocessor instruction712/2030000
 
INSTRUCTION ALIGNMENT712/2040000
 
INSTRUCTION FETCHING712/2050000
 
Of multiple instructions simultaneously712/2060000
 
Prefetching712/2070000
 
INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)712/2080000
 
Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)712/2090000
 
Decoding instruction to accommodate variable length instruction or operand712/2100000
 
Decoding instruction to generate an address of a microroutine712/2110000
 
Decoding by plural parallel decoders712/2120000
 
Predecoding of instruction component712/2130000
 
INSTRUCTION ISSUING712/2140000
 
Simultaneous issuance of multiple instructions712/2150000
 
DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/2160000
 
Scoreboarding, reservation station, or aliasing712/2170000
 
Commitment control or register bypass712/2180001
 
Reducing an impact of a stall or pipeline bubble712/2190000
 
PROCESSING CONTROL712/2200000
 
Arithmetic operation instruction processing712/2210000
 
Floating point or vector712/2220000
 
Logic operation instruction processing712/2230000
 
Masking712/2240000
 
Processing control for data transfer712/2250000
 
Instruction modification based on condition712/2260000
 
Specialized instruction processing in support of testing, debugging, emulation712/2270000
 
Context preserving (e.g., context swapping, checkpointing, register windowing712/2280000
 
Mode switch or change712/2290000
 
Generating next microinstruction address712/2300000
 
Detecting end or completion of microprogram712/2310001
 
Hardwired controller712/2320000
 
Branching (e.g., delayed branch, loop control, branch predict, interrupt)712/2330000
 
Conditional branching712/2340000
 
Simultaneous parallel fetching or executing of both branch and fall-through path712/2350000
 
Evaluation of multiple conditions or multiway branching712/2360000
 
Prefetching a branch target (i.e., look ahead)712/2370000
 
Branch target buffer712/2380000
 
Branch prediction712/2390000
 
History table712/2400000
 
Loop execution712/2410000
 
To macro-instruction routine712/2420000
 
To microinstruction subroutine712/2430000
 
Exeception processing (e.g., interrupts and traps)712/2440000
 
Processing sequence control (i.e., microsequencing)712/2450000
 
Plural microsequencers (e.g., dual microsequencers)712/2460000
 
Multilevel microcontroller (e.g., dual-level control store)712/2470000
 
Writable/changeable control store architecture712/2480000
 
BYTE-WORD REARRANGING, BIT-FIELD INSERTION OR EXTRACTION, STRING LENGTH DETECTING, OR SEQUENCE DETECTING712/3000000
 
FOREIGN ART COLLECTION7120
 
CLASS-RELATED FOREIGN DOCUMENTS712/FOR0000
 
ARRANGEMENTS FOR PROGRAM CONTROL, E.G., CONTROL UNIT (EPO)712/E090010
 
Using wired connections, e.g.,plugboard (EPO)712/E090021
 
Using stored program, i.e., using internal store of processing (EPO)712/E090030
 
Micro-control or micro-program arrangements (EPO)712/E090041
 
Execution means for micro-instructions irrespective of the micro-instruction function, e.g., decoding of micro-instructions and nano-instructions; timing of micro instructions; programmable logic arrays; delays and fan-out problems (EPO)712/E090050
 
Micro instruction function e.g., input/output micro-instruction; diagnostic micro-instruction; micro-instruction format (EPO)712/E090060
 
Loading of the micro-program (EPO)712/E090070
 
Enhancement of operational speed, e.g., by using several micro-control devices operating in parallel (EPO)712/E090080
 
Address formation of the next micro-instruction (EPO)712/E090090
 
Micro-instruction address formation(EPO)712/E090100
 
Arrangements for next micro-instruction selection (EPO)712/E090110
 
Micro-instruction selection based on results of processing (EPO)712/E090120
 
By address selection on input of storage (EPO)712/E090130
 
By instruction selection on output of storage (EPO)712/E090140
 
Micro-instruction selection not based on processing results, e.g., interrupt, patch, first cycle store, diagnostic programs (EPO)712/E090150
 
Arrangements for executing machine-instructions, e.g., instruction decode (EPO)712/E090160
 
Controlling the executing of arithmetic operations (EPO)712/E090170
 
Controlling the executing of logical operations (EPO)712/E090180
 
Controlling single bit operations (EPO)712/E090190
 
For comparing (EPO)712/E090200
 
For format conversion (EPO)712/E090210
 
Using storage based on relative movement between record carrier and transducer (EPO)712/E090220
 
Register arrangements, e.g., register files, special registers (EPO)712/E090230
 
Special purpose registers, e.g., segment register, profile register (EPO)712/E090240
 
Register structure, e.g., multigauged registers (EPO)712/E090250
 
Implementation provisions thereof, e.g., ports, bypass paths (EPO)712/E090260
 
Organization of register space, e.g., distributed register files, register banks (EPO)712/E090270
 
Instruction analysis, e.g., decoding, instruction word fields (EPO)712/E090280
 
Variable length instructions or constant length instructions whereby the relative length of operation and operand part is variable (EPO)712/E090290
 
Decoding the operand specifier, e.g., specifier format (EPO)Speech classification or search (EPO)712/E090300
 
With implied specifier, e.g., top of stack (EPO)712/E090310
 
For specific instructions not covered by the preceding groups, e.g., halt, synchronize (EPO)712/E090320
 
Controlling loading, storing, or clearing operations (EPO)712/E090330
 
Controlling moving, shifting, or rotation operations (EPO)712/E090340
 
With operation extension or modification (EPO)712/E090350
 
Using data descriptors, e.g., dynamic data typing (EPO)712/E090360
 
Using run time instruction translation (EPO)712/E090370
 
Addressing or accessing the instruction operand or the result (EPO)712/E090380
 
Of multiple operands or results(EPO)712/E090390
 
Indirect addressing (EPO)712/E090400
 
Indexed addressing (EPO)712/E090410
 
Using index register, e.g., adding index to base address (EPO)712/E090420
 
Using wraparound, e.g., modulo or circular addressing (EPO)712/E090430
 
Using scaling, e.g., multiplication of index (EPO)712/E090440
 
Concurrent instruction execution, e.g., pipeline, look ahead (EPO)712/E090450
 
Data or operand accessing, e.g., operand prefetch, operand bypass (EPO)712/E090460
 
Operand prefetch, e.g., prefetch instruction, address prediction (EPO)712/E090470
 
Maintaining memory consistency (EPO)712/E090480
 
Instruction issuing, e.g., dynamic instruction scheduling, out of order instruction execution (EPO)712/E090490
 
Speculative instruction execution, e.g., conditional execution, procedural dependencies, instruction invalidation (EPO)712/E090500
 
Using dynamic prediction, e.g., branch history table (EPO)712/E090510
 
Using static prediction, e.g., branch taken strategy (EPO)712/E090520
 
From multiple instruction streams, e.g., multistreaming (EPO)712/E090530
 
Of compound instructions (EPO)712/E090540
 
Instruction prefetch, e.g., instruction buffer (EPO)712/E090550
 
For branches, e.g., hedging branch folding (EPO)712/E090560
 
Using address buffers, e.g., return stack (EPO)712/E090570
 
For loops, e.g., loop buffer (EPO)712/E090580
 
With instruction modification, e.g. store into instruction stream (EPO)712/E090590
 
Recovery, e.g., branch miss-prediction, exception handling (EPO)712/E090600
 
Using multiple copies of the architectural state, e.g., shadow registers (EPO)712/E090610
 
Using instruction pipelines (EPO)712/E090620
 
Synchronization, e.g., clock skew (EPO)712/E090630
 
Technology-related problems thereof, e.g., GaAs pipelines (EPO)712/E090640
 
Pipelining a single stage, e.g., superpipelining (EPO)712/E090650
 
Using a slave processor, e.g., coprocessor (EPO)712/E090660
 
Which is not visible to the instruction set architecture, e.g., using memory mapping, illegal opcodes (EPO)712/E090670
 
For non-native instruction set architecture (EPO)712/E090680
 
Which is visible to the instruction set architecture (EPO)712/E090690
 
Having access to instruction memory (EPO)712/E090700
 
Using a plurality of independent parallel functional units (EPO)712/E090710
 
Decoding (EPO)712/E090720
 
Address formation of the next instruction, e.g., incrementing the instruction counter, jump (EPO)712/E090730
 
Program or instruction counter, e.g., incrementing (EPO)712/E090740
 
Branch or jump to non-sequential address (EPO)712/E090750
 
Unconditional, e.g., indirect jump (EPO)712/E090760
 
Conditional (EPO)712/E090770
 
For cyclically repeating instructions, e.g., iterative operation, loop counter (EPO)712/E090780
 
Condition code generation, e.g., status register (EPO)712/E090790
 
Selective instruction skip or conditional execution, e.g., dummy cycle (EPO)712/E090800
 
Sequential commutation, e.g., ring counter, cyclical pulse distribution (EPO)712/E090810
 
Arrangements for executing sub-programs, i.e., combinations of several instructions (EPO)712/E090820
 
Formation of sub-program jump address or of return address (EPO)712/E090830
 
Object Oriented Method Invocation (EPO)712/E090840
 
Optimizing for Receiver Type (EPO)712/E090850
 
Using record carriers containing only program instructions (EPO)712/E090860