http://www.peertopatent.org/patent/69/prior_art/list One embodiment of the present invention is a processor that processes inductive doubling SIMD instructions, which processor comprises: an Instruction Fetch Unit that loads a SIMD instruction and applies it as input to a SIMD Instruction Decode Unit; wherein the SIMD Instruction Decode Unit decodes the applied SIMD instruction and produces output signals including SIMD field width identification signals and one or more SIMD half-operand modifier signals. en-us Method and apparatus for an inductive doubling architecture Title: A High-Performance SIMD Floating Point Unit for BlueGene/L:Architecture, Compilation, and Algorithm <br/>ISBN: Proceedings of the 13th I<br/>Description: We describe the design, implementation, and evaluation of a dual-issue SIMD-like extension of the PowerPC 440 floating-point unit (FPU) core. It has several novel features, such as a computational crossbar and cross-load/store instructions, which enhance the performance of numerical codes. Tue, 03 Jun 2008 15:08:33 -0700 http://www.peertopatent.org/prior_art/208/detail Method and apparatus for an inductive doubling architecture Patent/Application #: US20060227966A1<br/>Description: According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand. Tue, 03 Jun 2008 14:52:02 -0700 http://www.peertopatent.org/prior_art/207/detail