Pre-Grant Publication Number: 20080046686
Filing Date: August 06, 2007
Inventors: Robert Cameron
Assignee: INTERNATIONAL CHARACTERS, INC.
Current U.S. Classification: 712, 712/022000, 712/E09002
View Prior Art for Claim 00005
The method of Claim 4 wherein:
the half-operand modification may be either a high half operand modification or a low half operand modification;
the high half-operand modification selects only the high n/2 bits of each n-bit field; and
the low half-operand modification selects only the low n/2 bits of each field.
Patent/Application # US20060227966A1
Description
According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.
Title A High-Performance SIMD Floating Point Unit for BlueGene/L:Architecture, Compilation, and Algorithm
ISBN Proceedings of the 13th I
Description
We describe the design, implementation, and evaluation
of a dual-issue SIMD-like extension of the PowerPC
440 floating-point unit (FPU) core.
It has several novel features, such as a computational crossbar and cross-load/store instructions,
which enhance the performance of numerical codes.
