Pre-Grant Publication Number: 20080046686
Filing Date: August 06, 2007
Inventors: Robert Cameron
Assignee: INTERNATIONAL CHARACTERS, INC.
Current U.S. Classification: 712, 712/022000, 712/E09002
View Prior Art for Claim 00004
A method for performing Single Instruction Multiple Data (SIMD) instructions on a processor wherein one or more data values of total size N bits are partitioned into j fields of size n bits, where N=j*n for some integer j≧1, and a single instruction is applied to each field of the j fields; wherein the method comprises:
modifying each of the j fields of the one or more data values according to a half-operand modification prior to applying the instruction; and
applying the instruction to each field of the j fields.
Title A High-Performance SIMD Floating Point Unit for BlueGene/L:Architecture, Compilation, and Algorithm
ISBN Proceedings of the 13th I
Description
We describe the design, implementation, and evaluation
of a dual-issue SIMD-like extension of the PowerPC
440 floating-point unit (FPU) core.
It has several novel features, such as a computational crossbar and cross-load/store instructions,
which enhance the performance of numerical codes.
