Pre-Grant Publication Number: 20080046686
Filing Date: August 06, 2007
Inventors: Robert Cameron
Assignee: INTERNATIONAL CHARACTERS, INC.
Current U.S. Classification: 712, 712/022000, 712/E09002
View Prior Art for Claim 00003
The processor of Claim 2 wherein the SIMD half-operand modifier signals comprise two signals for each operand, the first signal h having a first value whenever a high half-operand modification is to be applied to the operand value and another value otherwise, and the second signal having a first value whenever a low half-operand modification is to be applied to the operand value and another value otherwise.
Patent/Application # US20060227966A1
Description
According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.
Title A High-Performance SIMD Floating Point Unit for BlueGene/L:Architecture, Compilation, and Algorithm
ISBN Proceedings of the 13th I
Description
We describe the design, implementation, and evaluation
of a dual-issue SIMD-like extension of the PowerPC
440 floating-point unit (FPU) core.
It has several novel features, such as a computational crossbar and cross-load/store instructions,
which enhance the performance of numerical codes.
