According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.

We describe the design, implementation, and evaluation of a dual-issue SIMD-like extension of the PowerPC 440 floating-point unit (FPU) core. It has several novel features, such as a computational crossbar and cross-load/store instructions, which enhance the performance of numerical codes.