forming a plurality of cores for performing designed tasks to an integrated circuit;

embedding built-in self test (BIST) circuitry to each of the plurality of cores;

providing, to the integrated circuit, a programmable BIST controller having instructions for selectively invoking BIST operations via the BIST circuitry in each of the cores; and

determining which core to invoke BIST operations in and invoking BIST operations only in the determined cores.