a plurality of cores designed for performing a predetermined task, each of the plurality of cores having a built-in self test (BIST) engine for implementing BIST operations specific for the core;

a test access port for providing an interface for receiving input form an external controller, the input identifying cores to be tested; and

a programmable BIST controller, coupled to the plurality of cores and the test access port, the programmable BIST controller including BIST control and instructions for invoking BIST operations on cores identified via the input received via the test access port.