Pre-Grant Publication Number: 20070283129
Filing Date: December 28, 2005
Inventors: Stephan Jourdan, Avinash Sodani, Michael Fetterman, Per Hammarlund, Glenn Hinton
Assignee: Intel
Current U.S. Classification: 712, 712/004000, 712/E09004
View Prior Art for Claim 00016
A central processing unit (CPU) comprising:
an execution unit to execute a VL writer μop to set a VL value;
a vector length (VL) tracker to cause a first number of μops to be generated if the VL value is within a first range of values and to cause a second number of μops to be generated if the VL value is within a second range of values.
Title The microarchitecture of the IBM eServer z900 processor
Description
If would seem that the current invention is a specific instance of IF logic, and a
special case of logic first appearing in the IBM 360's TRT (TRanslate and Test)
instruction.
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