Pre-Grant Publication Number: 20070283129
Filing Date: December 28, 2005
Inventors: Stephan Jourdan, Avinash Sodani, Michael Fetterman, Per Hammarlund, Glenn Hinton
Assignee: Intel
Current U.S. Classification: 712, 712/004000, 712/E09004
View Prior Art for Claim 00010
A computer system comprising:
a main memory device to store a first and second instruction, each of which to be decoded into at least one μop having a corresponding vector length (VL) value, and
a central processing unit (CPU) to fetch the first instruction and to retire a first number of uops in response to decoding the second instruction, wherein the first number of uops depends upon the VL value of the at least one μop corresponding to the first instruction.
Title The microarchitecture of the IBM eServer z900 processor
Description
If would seem that the current invention is a specific instance of IF logic, and a
special case of logic first appearing in the IBM 360's TRT (TRanslate and Test)
instruction.
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