Pre-Grant Publication Number: 20070283129
Filing Date: December 28, 2005
Inventors: Stephan Jourdan, Avinash Sodani, Michael Fetterman, Per Hammarlund, Glenn Hinton
Assignee: Intel
Current U.S. Classification: 712, 712/004000, 712/E09004
View Prior Art for Claim 00001
A method comprising:
receiving a vector length (VL) value; and
generating a first number of micro-operations (μops) if the VL value is equal to or less than a first value and generating a second number μops if the VL value is greater than the first value.
Title The microarchitecture of the IBM eServer z900 processor
Description
If would seem that the current invention is a specific instance of IF logic, and a
special case of logic first appearing in the IBM 360's TRT (TRanslate and Test)
instruction.
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