Pre-Grant Publication Number: 20070260907
Filing Date: May 02, 2006
Inventors: Martin Dixon, Robert Greiner, Benjamin Chaffin
Assignee: Intel
Current U.S. Classification: 713, 713/500000
View Prior Art for Claim 00012
The apparatus of Claim 11, wherein the underflow condition is to be detected by performing a logical AND operation between the result of the subtraction and a logical NOR'ed version of the upper group of bits.
