http://www.peertopatent.org/patent/43/prior_art/list An arithmetic processing system is taught to be formed by combining a crossbar array with programming circuitry, input circuitry, and post-processing circuitry. The programming circuitry is configured to set crosspoints of the crossbar array to either a relatively high conductivity or a relatively low conductivity state corresponding to a logic 1 or logic 0, thereby programming at least one programmed numerical value into the crossbar array. The input circuitry provides a binary input representative of an input numerical value to columns of the crossbar array. The post-processing circuitry converts an analog output vector produced from the rows of the crossbar array into a binary output representative of an output numerical value mathematically related to the at least one programmed numerical value and the input numerical value. en-us Crossbar arithmetic processor Title: Logic Gates and Computation from Assembled Nanowire Building Blocks<br/>Description: The reference describes a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks (or crossbars). Further the reference describes that nanowire junction arrays (crossbars) have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computations. Tue, 08 Jan 2008 06:59:03 -0800 http://www.peertopatent.org/prior_art/135/detail Crossbar arithmetic processor Title: Nanoscale molecular-switch crossbar circuits<br/>Description: A crossbar memory unit with crosspoints programmable to low and high conductive states such that the crossbar array stores a bit pattern is disclosed. Tue, 08 Jan 2008 06:25:06 -0800 http://www.peertopatent.org/prior_art/134/detail Crossbar arithmetic processor Title: Array-Based Architecture for Molecular Electronics<br/>Description: We sketch a basic architecture for molecular electronics based on carbon nanotubes and silicon nanowires which can provide universal logic functionality with all logic and signal restoration operating at the molecular scale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging, bottom-up, nanoscale fabrication techniques. Tue, 08 Jan 2008 05:59:58 -0800 http://www.peertopatent.org/prior_art/133/detail Crossbar arithmetic processor Title: Digital Logic using Molecular Electronics<br/>Description: A reconfigurable architecture is based on chemically-assembled electronic nanotechnology (CAEN). A molecular latch based on molecular resonant tunneling diodes (RTDs) provides I/O-isolation, voltage restoration, and high fan-out. Moreover, a nanoblock based on CAEN has been used to implement a AND, OR, XOR gate to achieve computational objectives. Tue, 08 Jan 2008 05:39:15 -0800 http://www.peertopatent.org/prior_art/132/detail Crossbar arithmetic processor Title: The CMOS/Nano Interface from a Circuits Perspective<br/>Description: The publication describes crossbar based nanoelectronics, CMOS/nano interface and CMOS interface circuitry. The publication further describes simulation of crossbar nano circuitry having logic and arithmetic implementations. Tue, 08 Jan 2008 05:29:29 -0800 http://www.peertopatent.org/prior_art/131/detail Crossbar arithmetic processor Title: Evolution in Materio: Exploiting the Physics of Materials for Computation <br/>Description: The idea of using an array of programmable resistances to perform mathematical operations is disclosed. Sat, 05 Jan 2008 07:21:18 -0800 http://www.peertopatent.org/prior_art/127/detail Crossbar arithmetic processor Title: Defect-tolerant Logic with Nanoscale Crossbar Circuits<br/>Description: The application of a crossbar as an arithmetic processor (for adding binary numbers) is disclosed. Sat, 05 Jan 2008 07:02:41 -0800 http://www.peertopatent.org/prior_art/126/detail Crossbar arithmetic processor Title: Defect-tolerant Logic with Nanoscale Crossbar Circuits<br/>Description: The application of a crossbar as an arithmetic processor (for adding binary numbers) is disclosed. Sat, 05 Jan 2008 07:02:01 -0800 http://www.peertopatent.org/prior_art/125/detail Crossbar arithmetic processor Patent/Application #: US 2005/0258872 A1<br/>Description: An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances. Sat, 05 Jan 2008 03:56:40 -0800 http://www.peertopatent.org/prior_art/124/detail Crossbar arithmetic processor Patent/Application #: US5010505<br/>Description: The US granted patent describes an optical crossbar arithmetic/logic technique for logic and arithmetic operations. Sat, 05 Jan 2008 03:28:18 -0800 http://www.peertopatent.org/prior_art/123/detail Crossbar arithmetic processor Patent/Application #: EP1331671A1<br/>Description: The publication discloses a computing device for performing arithmetical operations, using an array of programmable resistances. Sat, 05 Jan 2008 02:58:10 -0800 http://www.peertopatent.org/prior_art/122/detail