http://www.peertopatent.org/patent/20070174746/activity A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors. en-us Tuning core voltages of processors With the advent of multi-core processors like the Intel Core 2 Duo and motherboards supporting a feature called automatic over clocking, such as Asus's BIOS automatic over clock which finds stable clock settings and voltage settings for multiple processors. This is also done with Ai Booster using multiple reboots. This patent really does not offer anything new especially when additionally considering the fact that the cores (considered separate processors) are operating in lock-step fashion already with respect to varying clock speeds and vCore values (Intel Speedstep). Must submit sources... Sat, 10 Nov 2007 22:19:24 -0800 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Rather than saying 'not offer anything new', I'd rather say that the claims are too broad and seem to include prior art with respect to software running on mainboard circuits external to the processor to manage multiple processors and memory. The claims must be more specific as the current claims mention processor, which technically a Core-2 Duo of the quad core variety such as the one in this very PC (Extreme Edition 2.66 Quad) have two separate processors with two cores - all operating lock step with respect to the motherboards's automatic overclock software. Sat, 10 Nov 2007 23:02:23 -0800 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors The wording of claim 1 is too ambiguous (varying, adjusting…) making the scope of claim 1 too broad and unclear. In my opinion, the wording of claim 8 is better, making the claim more specific and more clear and the scope is more or less the same. Thu, 04 Oct 2007 02:49:20 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors It is standard practice in integrated circuit test to 'find the Vdd' at which a component can operate at. These days, that discovered Vdd, or range of Vdds, is often hard coded into the device as a 'voltage ID'. Laser fuses have been used in the past for such personalization, electronic fuses are used most often at present. See any post 2005 (or even earlier) Intel databook for any of their Pentium-type processors, as just one of many examples. I don't think that having the computer system (instead of integrated circuit test equipment) discover such ranges of Vdd operation makes it novel. Wed, 05 Sep 2007 13:16:42 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Matt, Great observations, but just to clarify patent lingo, claiming a process where the computer system instead of integrated circuit test equipment discover Vdd ranges would make an invention "novel" (35 USC 102) in the sense that it was different. I think what you meant to say is that having a computer system discover Vdd ranges would be obvious (35 USC 103) to a person of ordinary skill in the art in light of the fact that it is well known to have integrated circuit test equiment discover such ranges. To help support this argument, you might want to scan and submit the approriate pages from an Intel data book. Your argument would be further strengthened if you could post an example of where someone implemented a procedure normally done on test equipment directly into a computer system. The examiner would then find the claim obvious in light of the Intel reference and further in view of the computer implementation reference. Thu, 06 Sep 2007 05:17:30 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Thanks Mark, I understand what you are saying regarding 35 USC 103. I think I can find the two types of documentation you are describing. Thu, 06 Sep 2007 05:26:03 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Here is an Intel databook with pertinent information about IC manufacturers discovering the range of power supply operation for a device: http://download.intel.com/design/Pentiumd/datashts/30750603.pdf See pp15-17. Specifically, in section 2.3, paragraph 2, the following: "Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 2-3." Here is a reference to the use of logic built in self test ('lbist', which is normally done on test equipment) in a computer system environment: In-system failure investigation on 0.18 /spl mu/m high speed serial link ASIC using logic built-in self test Mechler, J.T.; Bulaga, R.; Garlett, J.; Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003 21-24 Sept. 2003 Page(s):613 - 616 Here is another similar reference, where the introduction describes the use of lbist at all levels of the manufacturing process, including computer system test: 99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor Kusko, M.P.; Robbins, B.J.; Koprowski, T.J.; Huott, W.V.; Test Conference, 2001. Proceedings. International 30 Oct.-1 Nov. 2001 Page(s):586 - 592 Digital Object Identifier 10.1109/TEST.2001.966677 Fri, 21 Sep 2007 06:54:59 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Matt, These look like great references. If you an upload copies to the prior art section, then we can start matching them up to the specific limitations of the claims. Fri, 21 Sep 2007 07:07:31 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors http://web.archive.org/web/20070508055649/http://www.thegalleryofoldiron.com/SAGE.HTM above is a description of the SAGE computer of the 1950's, having a dual processor. The author says the would work "simultaneously" in high alert situations. Voltage margin testing was done routinely on each, under program control. The URL, however, is not dated, so can not be used as a reference. http://ed-thelen.org/SageIntro.html Above are copies from a manual, INTRODUCTION TO AN/FSQ-7 COMBAT DIRECTION CENTRAL AND AN/FSQ-8 COMBAT CONTROL CENTRAL 1 January 1959 - 15 March 1965 That discusses duplexing of "common" components, with voltage margine testing being done.. e.g., "Marginal checking (MC) is the method used to detect imminent circuit failures. The circuits are designed so that one or more of their associated supply voltage may be varied in prescribed amounts without causing circuit failure when the components are within accepted tolerances. Components outside of accepted tolerance require less voltage variation than normal to cause failure. Therefore, component deterioration can be detected by the amount of voltage variation required to cause failure. The voltage variation which causes circuit to fail is called the circuit margin. Marginal checking is not a maintenance tool, however, unless used with programs which operate the circuit to which the MC voltage excursions are applied. The MC System serves to vary the MC voltages one at a time, over large sections of the system. For a more detailed reliability check, a breakdown of these large circuit groups is made on the expected circuit margins. A further breakdown is provided for the purposes of fault isolation in the event of a failure during a reliability test. " This reference, however lacks "simultaneous" or "lockstep" Thu, 30 Aug 2007 13:58:52 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors archive.org urls have their dates of the archive in the url. This is a link to the same page from July 14, 2004. It counts as prior art since the date of archiving is prior to the priority date of the application http://web.archive.org/web/20040714120817/http://www.thegalleryofoldiron.com/SAGE.HTM Thu, 30 Aug 2007 16:15:40 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Mark, I had checked the "archive". Seems that the author has added material over time. The July 14, 2004 version did not have any details regarding the "A" and "B" computers operating simultaneously, or the voltage margin checks. Those were not added til May 2007. Fri, 31 Aug 2007 05:54:44 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors Good point. I should have checked more carefully. Fri, 31 Aug 2007 06:24:46 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors I'd be interested in learning just how fault tolerant these systems are. If they really set a new standard in error free computing in critical applications, there may be some interesting markets for it. It's tough to tell from the specification, however, since no experimental data is given. Wed, 29 Aug 2007 19:43:23 -0700 http://www.peertopatent.org/patent/20070174746/discussion Tuning core voltages of processors I'd be interested in learning just how fault tollerant these systems are. If they really set a new standard in error free computing in critical applications, there may be some interesting markets for it. It's tough to tell from the specification, however, since no experimental data is given. Wed, 29 Aug 2007 19:41:39 -0700 http://www.peertopatent.org/patent/20070174746/discussion