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    <title>Prior Art submitted for Tuning core voltages of processors</title>
    <link>http://www.peertopatent.org/patent/32/prior_art/list</link>
    <description>A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.</description>
    <language>en-us</language>
    <item>
      <title>A Low-Power Microcontroller with On-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications</title>
      <category>Tuning core voltages of processors</category>
      <description>Title: A Low-Power Microcontroller with On-Chip Self-Tuning  Digital Clock-Generator for Variable-Load Appl&lt;br/&gt;ISBN: &lt;br/&gt;Description: This paper describes a processor, controller, and machine readable description for processor tuning.  It is tuning clock speed at constant voltage, but this would be commonly recognized to pertain to voltage tuning at constant speed.</description>
      <pubDate>Wed, 26 Sep 2007 23:32:04 -0700</pubDate>
      <guid>http://www.peertopatent.org/prior_art/83/detail</guid>
    </item>
    <item>
      <title>Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation</title>
      <category>Tuning core voltages of processors</category>
      <description>Title: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation&lt;br/&gt;ISBN: &lt;br/&gt;Description: Another description of the RAZOR architecture.  Instead of a plurality of processors, it has one with a plurality of latches.  This is better in some ways than the proposed architecture (since the overhead is smaller) , and it could be argued it is a small step, clear to those educated in the art, between 1 processors with two sets of latches, and two processors running in lockstep.</description>
      <pubDate>Wed, 26 Sep 2007 22:52:44 -0700</pubDate>
      <guid>http://www.peertopatent.org/prior_art/82/detail</guid>
    </item>
    <item>
      <title>Making Typical Silicon Matter with Razor</title>
      <category>Tuning core voltages of processors</category>
      <description>Title: Computer&lt;br/&gt;ISBN: &lt;br/&gt;Description: A codesign methodology incorporates timing speculation into a low-power micropocessor pipeline and shaves energy levels far below the point permitted by worst-case computation paths</description>
      <pubDate>Wed, 29 Aug 2007 19:29:12 -0700</pubDate>
      <guid>http://www.peertopatent.org/prior_art/67/detail</guid>
    </item>
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