Pre-Grant Publication Number: 20070174746
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Prior Art (3)
Title Computer
ISBN
Description
A codesign methodology incorporates timing speculation into a low-power micropocessor pipeline and shaves energy levels far below the point permitted by worst-case computation paths
Title A Low-Power Microcontroller with On-Chip Self-Tuning Digital Clock-Generator for Variable-Load Appl
ISBN
Description
This paper describes a processor, controller, and machine readable description for processor tuning. It is tuning clock speed at constant voltage, but this would be commonly recognized to pertain to voltage tuning at constant speed.
Title Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
ISBN
Description
Another description of the RAZOR architecture. Instead of a plurality of processors, it has one with a plurality of latches. This is better in some ways than the proposed architecture (since the overhead is smaller) , and it could be argued it is a small step, clear to those educated in the art, between 1 processors with two sets of latches, and two processors running in lockstep.
