Pre-Grant Publication Number: 20070174746
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I don't think that having the computer system (instead of integrated circuit test equipment) discover such ranges of Vdd operation makes it novel.
Great observations, but just to clarify patent lingo, claiming a process where the computer system instead of integrated circuit test equipment discover Vdd ranges would make an invention "novel" (35 USC 102) in the sense that it was different.
I think what you meant to say is that having a computer system discover Vdd ranges would be obvious (35 USC 103) to a person of ordinary skill in the art in light of the fact that it is well known to have integrated circuit test equiment discover such ranges.
To help support this argument, you might want to scan and submit the approriate pages from an Intel data book. Your argument would be further strengthened if you could post an example of where someone implemented a procedure normally done on test equipment directly into a computer system.
The examiner would then find the claim obvious in light of the Intel reference and further in view of the computer implementation reference.
http://download.intel.com/design/Pentiumd/datashts/30750603.pdf
See pp15-17. Specifically, in section 2.3, paragraph 2, the following:
"Individual processor VID values may be calibrated during manufacturing such that two devices at
the same core speed may have different default VID settings. This is reflected by the VID Range
values provided in Table 2-3."
Here is a reference to the use of logic built in self test ('lbist', which is normally done on test equipment) in a computer system environment:
In-system failure investigation on 0.18 /spl mu/m high speed serial link ASIC using logic built-in self test
Mechler, J.T.; Bulaga, R.; Garlett, J.;
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
21-24 Sept. 2003 Page(s):613 - 616
Here is another similar reference, where the introduction describes the use of lbist at all levels of the manufacturing process, including computer system test:
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
Kusko, M.P.; Robbins, B.J.; Koprowski, T.J.; Huott, W.V.;
Test Conference, 2001. Proceedings. International
30 Oct.-1 Nov. 2001 Page(s):586 - 592
Digital Object Identifier 10.1109/TEST.2001.966677
These look like great references. If you an upload copies to the prior art section, then we can start matching them up to the specific limitations of the claims.
above is a description of the SAGE computer of the 1950's, having a dual processor. The author says the would work "simultaneously" in high alert situations. Voltage margin testing was done routinely on each, under program control. The URL, however, is not dated, so can not be used as a reference.
http://ed-thelen.org/SageIntro.html
Above are copies from a manual, INTRODUCTION
TO
AN/FSQ-7
COMBAT DIRECTION CENTRAL
AND
AN/FSQ-8
COMBAT CONTROL CENTRAL
1 January 1959 -
15 March 1965
That discusses duplexing of "common" components, with voltage margine testing being done.. e.g.,
"Marginal checking (MC) is the method used to detect imminent circuit failures. The circuits are designed so that one or more of their associated supply voltage may be varied in prescribed amounts without causing circuit failure when the components are within accepted tolerances. Components outside of accepted tolerance require less voltage variation than normal to cause failure. Therefore, component deterioration can be detected by the amount of voltage variation required to cause failure. The voltage variation which causes circuit to fail is called the circuit margin. Marginal checking is not a maintenance tool, however, unless used with programs which operate the circuit to which the MC voltage excursions are applied.
The MC System serves to vary the MC voltages one at a time, over large sections of the system. For a more detailed reliability check, a breakdown of these large circuit groups is made on the expected circuit margins. A further breakdown is provided for the purposes of fault isolation in the event of a failure during a reliability test. "
This reference, however lacks "simultaneous" or "lockstep"
http://web.archive.org/web/20040714120817/http://www.thegalleryofoldiron.com/SAGE.HTM