Pre-Grant Publication Number: 20070174746
Filing Date: December 20, 2005
Inventors: Juerg Haefliger, William Bruckert, James Klecka
Assignee: HEWLETT PACKARD COMPANY
Current U.S. Classification: 714, 714/721000
View Prior Art for Claim 00007
The method of Claim 1 further comprising, raising and lowering the core voltages of the plural processors to determine voltages where failures occur in order to calculate the operating range.
Title Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
ISBN
Description
Another description of the RAZOR architecture. Instead of a plurality of processors, it has one with a plurality of latches. This is better in some ways than the proposed architecture (since the overhead is smaller) , and it could be argued it is a small step, clear to those educated in the art, between 1 processors with two sets of latches, and two processors running in lockstep.
