http://www.peertopatent.org/patent/22/prior_art/list An apparatus and method for prefetching based on register tracking is disclosed. In one embodiment, an apparatus includes a register tracker and a pre-computation engine. The register tracker is to generate a pre-computation slice. The pre-computation engine is to execute the pre-computation slice. en-us Register tracking for speculative prefetching Patent/Application #: 5933630<br/>Description: Program launch acceleration using cache Thu, 26 Jul 2007 15:07:47 -0700 http://www.peertopatent.org/prior_art/34/detail Register tracking for speculative prefetching Title: ACM SIGARCH Computer Architecture News , Proceedings of the 27th annual international symposium on C<br/>ISBN: <br/>Description: The authors of this paper describe the approach of [[claim 8]]. [[Early load address resolution via register tracking]] Tue, 03 Jul 2007 12:14:55 -0700 http://www.peertopatent.org/prior_art/30/detail Register tracking for speculative prefetching Title: Understanding the Backward Slices of Performance Degrading Instructions<br/>ISBN: <br/>Description: For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early. Thu, 28 Jun 2007 12:25:32 -0700 http://www.peertopatent.org/prior_art/29/detail Register tracking for speculative prefetching Patent/Application #: 5,784,589<br/>Description: This submission targets the use of a tracking register. Wed, 20 Jun 2007 09:15:32 -0700 http://www.peertopatent.org/prior_art/19/detail