Pre-Grant Publication Number: 20070118696
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Prior Art (4)
#34us patent number 5933630
Applies to Claims 1,10,15,2,3,4,5,8
Submitted by: Juliana AgonCreated: about 1 year ago
Patent/Application # 5933630
Description
Program launch acceleration using cache
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Patent/Application # 5,784,589
Description
This submission targets the use of a tracking register.
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Submitted by: Keith O'NeilLast updated: about 1 year ago
Title ACM SIGARCH Computer Architecture News , Proceedings of the 27th annual international symposium on C
ISBN
Description
The authors of this paper describe the approach of [[claim 8]]. [[Early load address resolution via register tracking]]
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Submitted by: Matthew ZehrerCreated: about 1 year ago
Title Understanding the Backward Slices of Performance Degrading Instructions
ISBN
Description
For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early.
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