Program launch acceleration using cache

The authors of this paper describe the approach of [[claim 8]]. [[Early load address resolution via register tracking]]

For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early.

This submission targets the use of a tracking register.