Pre-Grant Publication Number: 20070118696
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Discussion (15)
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This will also make it easier for the reader to understand the discussion of that claim and to rate it.
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because it discusses some aspect of tracking that then allows speculative precomputation. See it at:
http://www.intel.com/research/mrl/library/148_collins_j.pdf
Interpreter for stack-based languages
United States Patent 6205578
Issued March 20, 2001
Inventor Daniel D. Grove
http://www.patentstorm.us/patents/6205578.html
Method and apparatus employing lookahead to reduce memory bank contention for decoupled operand references
United States Patent 5323489
Issued March 20, 2001
Inventor Daniel D. Grove
http://www.patentstorm.us/patents/5323489.html
Anyways, just my ideas on a place to start.
- using a second program (helper threads) in a multi-threaded processor to warm-up caches
- having hardware that runs ahead of the main thread to get data (decoupled access execute)
- using stride based prefetching
- automatically loading data when an address is stored into a register (CDC6600!)
I would focus on the how the ART is used to generate a p-slice; the section from "figure 2 illustrates..." to "figure 3 illustrate
technique described in this patent application, enables numerous types of prefetch access patterns used by a processor to prefetch data and/or instructions, so as to help increase the number of prefetched data and/or instructions that are actually used by the processor during the course of program execution, while redu