Pre-Grant Publication Number: 20070118696
Filing Date: November 22, 2020
Inventors: Donald McCauley, Sresth Kumar
Assignee: Intel Corporation
Current U.S. Classification: 711, 711/137000
View Prior Art for Claim 00001
An apparatus comprising:
a register tracker to generate a pre-computation slice; and
a pre-computation engine to execute the pre-computation slice.
Patent/Application # 5,784,589
This submission targets the use of a tracking register.
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Title Understanding the Backward Slices of Performance Degrading Instructions
For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early.
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#34us patent number 5933630
Applies to Claims 1,10,15,2,3,4,5,8
Submitted by: Juliana AgonCreated: about 1 month ago
Patent/Application # 5933630
Program launch acceleration using cache
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